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Method for a multisided ceramic capacitor

IP.com Disclosure Number: IPCOM000009886D
Publication Date: 2002-Sep-25
Document File: 3 page(s) / 40K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a low inductance multisided ceramic capacitor.

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Method for a multisided ceramic capacitor

Disclosed is a method for a low inductance multisided ceramic capacitor.

Background

        � � � � � A requirement exists for a low-inductance ceramic capacitor to support future microprocessor platforms.

        � � � � � Conventionally, ceramic capacitors are limited in form and factor to parallepiped shapes with terminations on a maximum of four sides (see Figure 1).

General description

        � � � � � The disclosed method describes a surface-mount low-inductance ceramic capacitor with multisided symmetrically placed terminations. An improvement in assembly is expected due to better-balanced reflow forces.

        � � � � � The key elements of the disclosed method include:

•        � � � � SMT capability

•        � � � � Ceramic-type material

•        � � � � Ni-plated and tin/solder-plated terminations

•        � � � � Multiple terminations in a symmetrical layout

•        � � � � Capacitance value based on the internal layer design

•        � � � � Inductance canceling due to current flow through multiple adjacent terminals

Advantages

        � � � � � The disclosed method provides advantages, including:

·        Improved performance due to an increased number of terminations that provide current-canceling effects, minimizing the self-inductance of the capacitor

·        Improved assembly due to better-balanced reflow forces.

        � � � � �

Detailed description

        � � � � � The disclosed method is a ceramic chip capacitor with multisided symmetrically placed terminations where the number of terminations can vary....