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Method for reducing power in the HALT and STOP GRANT CPU states

IP.com Disclosure Number: IPCOM000009890D
Publication Date: 2002-Sep-25
Document File: 5 page(s) / 121K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for reducing power in the HALT and STOP GRANT CPU states. Benefits include improved power performance.

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Method for reducing power in the HALT and STOP GRANT CPU states

Disclosed is a method for reducing power in the HALT and STOP GRANT CPU states. Benefits include improved power performance.

Background

              Power management and energy costs are becoming increasingly important in contemporary PC platforms, both in desktop and mobile applications. With the increasing use of bus-master devices in the platform (such as USB and AC97), the CPU conducts an increasing number of snoops in the HALT (C1) and STOP GRANT (C2) states.

              C1 is a state entered by a CPU when it executes a HALT instruction. The C2 state is entered when the software writes to a register in the chipset, which is specified in the Advanced Configuration and Power Interface (ACPI) specification. Writing to a register in the chipset triggers the chipset to pull the STPCLK# pin on the CPU, initiating the STOP GRANT state.

              In both the cases, the CPU stops executing instructions and enters a low-power state in which clocks to most parts of the CPU are turned off. The CPU stays in this mode until the platform discontinues the driving of the STPCLK# pin (in case of C2) or gets a break event from the HALT state (such as an interrupt).

              In conventional implementations, the clock grid is running during the C1 and C2 states. With some systems, clock-grid power is significant, 15-20W. Turning the clock grid off is not trivial because certain parts of the chip (such as the bus cluster) must receive the clock to be able to monitor the signals on the bus to service snoops. The feedback path to keep the core PLL locked is taken from the far end of the clock distribution network (see Figure 1). When the clock grid is shut off, the core PLL is shut off if no special processing is required. Shutting off the core PLL is not an option in this state because it adds too much latency to service the snoops (5-10 µs).

              In conventional implementations, all the clocks are turned on during a snoop event.

General description

              The disclosed method is a set of techniques to reduce the power in two of the idle states in a CPU. Specifically, the two idle states are the C1 (HALT) state and the C2 (STOP GRANT) state.

              The portions of the CPU that monitor and control the state transitions and the break events remain on in the C2 state. The power consumed by this logic, the power in the global clock grid, and the leakage power consumed by the CPU are the components that determine the total power usage of the CPU in the C1/C2 state.

              The disclosed method (see Figure 1) includes three techniques that can be implemented independently:

•             Frequency/voltage reduction in C1/C2 state

•             Shutting off the global clock distribution grid

•             Selective power up of sections of chip to service snoops from C1/C2

Advantages

              The disclosed method provides advantages, including:

•             Improved power performance due to only turnin...