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Method for a high performance voltage translating differential amplifier

IP.com Disclosure Number: IPCOM000009894D
Publication Date: 2002-Sep-25
Document File: 5 page(s) / 117K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a high performance voltage translating differential amplifier. Benefits include improved performance, improved design simplicity, and improved design flexibility.

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Method for a high performance voltage translating differential amplifier

Disclosed is a method for a high performance voltage translating differential amplifier. Benefits include improved performance, improved design simplicity, and improved design flexibility.

Background

              With conventional silicon manufacturing processes, core supply voltages are typically lower than those of input/output systems, such as peripheral component interface (PCI) and double data rate (DDR) synchronous dynamic random access memory (SDRAM) busses. This situation occurs because newer processes have smaller devices that can only withstand very low voltage swings. The circuits that receive signals from the external buses must be tolerant to higher input voltage swings and perform a voltage domain translation on these signals to safely propagate them to the core. At the same time, gain and bandwidth must be maximized for these circuits due to the high speed of the bus (100 MHz or more).

              The conventional method, resistance capacitance (RC) dividers, is a source of on-die leakage (see Figure 1). RC dividers are subject to manufacturing mismatches that corrupt the incoming signals and reduce design margins. Moreover, on-die capacitors do not scale with the process as predictably as active devices.

              Another conventional solution is high voltage tolerant devices. However, they have higher threshold voltages and offer poor performance. Therefore, a receiver design with only high voltage tolerant devices would undergo serious challenges for both bandwidth and gain.

 

General description

              The disclosed method is a differential amplifier that functions as a receiver for general-purpose busses, such as DDR-SDRAM or PCI. The disclosed method has the following features:

•             Two-stage architecture followed by a digital buffer

•             Positive-channel metal oxide semiconductors (PMOS) differential pair input

•             PMOS Cascade

•             Dual negative-channel metal oxide semiconductors (NMOS) load

•             Self-biased second stage powered with a low voltage core supply

•             High bandwidth coverage

Advantages

              Some implementations of the structure and method provide one or more of the following advantages:

•             Improved performance due to higher bandwidth and the voltage translation capability required for I/O busses

•             Improved design simplicity due to one compact and reasonably simple circuit

•             Improved design flexibility due to improved scalability

•             Improved power performance due to and absolute worst case current consumption of 3mA, with an...