Filtering out Repetitive Errors During Simulation-Based Verification of an IC Layout
Publication Date: 2002-Oct-01
The IP.com Prior Art Database
An approach to better handling repettive errors reported during simulation-based verification of an integrated circuit layout is described. This reduces the manual review, or inspection, time spent on going through the output of the verification.
FILTERING OUT REPETITIVE ERRORS
5 DURING SIMULATION-BASED
VERIFICATION OF AN IC LAYOUT
correction, have been applied to the layout, the layout can be verified through a simulation-based verification process to ensure that errors will not arise during a subsequent manufacturing process. This simulation-based verification process generates a list of potential errors that are manually inspected by a user to determine whether the potential errors need to be corrected. In some
embodiments the SiVL(R) software licensed by Numerical Technologies, Inc., San Jose, California can be used to perform the verification process.
Unfortunately, as integrated circuit layouts continue to increase in size, more potential errors are being detected. Consequently, this manual
Field of the Invention
The invention relates to the process of fabricating semiconductor chips. More specifically, the invention relates to a method and an apparatus for filtering out repetitive errors that are manually inspected or reviewed during
simulation-based verification of an integrated circuit layout.
After the layout of an integrated has been generated, and after resolution enhancement techniques, such as phase shifting and optical proximity
inspection process can take many hours, and possibly even days. During this manual inspection process, the user typically examines a large number of errors that are similar in structure. This means that the user wastes a great deal of time examining minor variations of the same error over and over again.
Existing systems attempt to remedy this problem by using a cell-
based technique to suppress repeated instances of the same error that occur in other instances of the same cell. However, this cell-based technique only works for identical cells located in identical environments, and does not catch errors that occur in cells that are similar structure or have similar environments. Nor does this approach catch the same error repeated inside a given cell. Moreover, the
relatively shallow hierarchical structure of some post-OPC layouts makes it hard to determine if specific structures are similar to each other from the hierarchy information.
Hence, what is needed is a method and an apparatus that eliminates the need for the user to repeatedly inspect similar errors during a simulation-based
based verification process. This can be done in a number of ways.
Referring to FIG. 1, while scanning through a list of errors flagged by the simulation-based verification process, the system retrieves an error (step
102). Next, the system determines if the error has been seen before (step 104). This is accomplished by comparing geometrical features associated with the error
against geometrical features associated with errors that have been seen before.
If the system determines the error has not been seen before, the system displays the error to the...