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Method for two-phase voltage identification signaling Disclosure Number: IPCOM000009973D
Publication Date: 2002-Oct-02
Document File: 6 page(s) / 350K

Publishing Venue

The Prior Art Database


Disclosed is a method for two-phase voltage identification (VID) signaling. Benefits include improved performance and improved throughput.

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Method for two-phase voltage identification signaling

Disclosed is a method for two-phase voltage identification (VID) signaling. Benefits include improved performance and improved throughput.

General description

        � � � � � The disclosed method is two-phase voltage identification signaling to provide an interface to the core voltage regulator, enabling a larger set of VID codes with fewer signals than a direct parallel interface. The method requires less interface logic complexity, development, and validation than a conventional serial interface.


        � � � � � Some implementations of the disclosed structure and method provide one or more of the following advantages:

•        � � � � Improved performance due to increased voltage resolution and range

•        � � � � Improved throughput due to increased silicon bin-split

•        � � � � Improved cost performance due to reduced platform cost

Detailed description

        � � � � � Two-phase voltage identification signaling is a communication interface between a semiconductor device and a voltage regulator. This interface achieves a larger number of VID codes than direct parallel communication while using the same number of interface signals. The method does not involve the interface complexity of a conventional serial communication interface.

        � � � � � The communication interface consists of the following signals and their functions with the connections (see Figure 1):

•        � � � � VID [0:4]: VID signals that carry the voltage code. CPU output occurs when the VRM input is latched twice on falling and rising edges. The first latch is a low VID on a falling edge. This latch selects the fine resolution voltage. The second latch is a high VID on a rising edge. This latch selects the general voltage operating point.

•        � � � � VID_HI/LOW#: VID code (high or low) that is being driven/latched. When the signal is low, the value is the low VID. When the signal is high, the value is the high VID. CPU output is voltage regulator module (VRM) input.

•        � � � � VID_change#: Edge latch signal to the voltage regulator (VR). The high VID occurs on
the falling edge. The low VID occurs on the rising edge. CPU output is VRM input. All signals are ignored by the VRM when this signal is inactive. The change number puts the VR into a soft-start condition.

•        � � � � Vcore_PWRGD: VID code that has been latched and it indicates the Vcore is within acceptable limits. VRM output is CPU input. This signal handshakes to the processor to indicate a stable voltage for operation. This signal is not the same as VRM_PWRGD, which must stay asserted during a VID change to maintain the platform status.

        � � � � � Due to the double bit value of a VID signal, any increase to the number of VID bits provides a four-times multiplier. For example, an increase of 5 VID lines is 210 codes (1024 codes). With 6 VID lines, the increase is 212 codes (4096 codes). By having more VID codes, the voltage range and voltage granularity (mV per code) can be improve...