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Method for an in-line 8/2/2 bump-out pattern for high-speed serial interfaces

IP.com Disclosure Number: IPCOM000010018D
Publication Date: 2002-Oct-09
Document File: 5 page(s) / 236K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for an in-line 8/2/2 bump-out pattern for high-speed serial interfaces. Benefits include improved performance.

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Method for an in-line 8/2/2 bump-out pattern for high-speed serial interfaces

Disclosed is a method for an in-line 8/2/2 bump-out pattern for high-speed serial interfaces. Benefits include improved performance.

Background

        � � � � � Because the north bridge runs at a very high frequency, flip-chip ball grid array (FCBGA) packages are typically used for memory control hub (MCH) chipset packaging. In FCBGA packages, bumps are media between the silicon and the package substrate, which provide electrical connections and determine the silicon layout and the silicon size. Conventional bump-out patterns for all previous FCBGA products are staggered on diagonal lines, also called face centered squares (FCSs, see Figure 1).

        � � � � � Due to the high density of I/O counts on silicon and differential signaling routing, 8 signal bumps (2 transceivers) must be placed on the silicon within an area 387.36-µm wide. With the FCS bump-out pattern, the minimum distance from the edge of the silicon to the edge of the last signal buffer is 1628 µm, which is larger than the active circuit area (~1400 µm). This extra area cannot be used efficiently because the active circuitry must reside on top of the signal bumps for optimal performance. In addition, the extra area will make the capacitance of routing from the buffers to the corresponding bumps on the silicon very difficult to control less than 1.5 pF, which is the design requirement from an electrical performance perspective. Return loss is directly impacted by the amount of pad capacitance.

General description

        � � � � � The disclosed method is an in-line bump-out pattern designed for the PCI Express interface to resolve the issues mentioned above. The goal of this design is to reduce the bump routing capacitance of the silicon and optimize the silicon area required to layout the circuits efficiently. The in-line bump pattern can increase I/O counts per mm2 by 18% compared to the FCS bump pattern, which significantly reduces the silicon size. By using the disclosed method, one additional p...