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Method for a noise-immune passgate MUX-latch

IP.com Disclosure Number: IPCOM000010031D
Publication Date: 2002-Oct-09
Document File: 2 page(s) / 159K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a noise-immune passgate MUX-latch. Benefits include improved performance and noise susceptibility.

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Method for a noise-immune passgate MUX-latch

Disclosed is a method for a noise-immune passgate MUX-latch. Benefits include improved performance and noise susceptibility.

Background

        � � � � � Increased chip speed leads to increased noise that can cause the chip to fail. In many cases, noise susceptibility limits the speed. A structure that is conventionally used in circuits is a MUX-latch, which is a multiplexer and a latch in a single structure.

        � � � � � Conventional MUX-latches process several inputs using the following handlers:
1.        � � Inverter
2.        � � Passgate
3.        � � Common node with a sustainer element
4.        � � Inverter that drives the output

        � � � � � The first inverter is especially important when the input driver is far away, and the network is susceptible to noise. If the inverter is omitted, bootstrap noise can propagate to the sustained node and change its value.

        � � � � � The keeper input voltage of the conventional MUX-latch structure is affected by the noise propagated from the mx node to the fb node through the feed back transistor (see Figure 1).

General description

        � � � � � The disclosed method isolates the sustained node from the MUX node. This enables omitting of the input inverter and removes the output driver if sizing allows. This structure reduces the path by two inversions, making a much faster circuit.

Advantages

        � � � � � The disclosed method provides advantages, including improved performance due to increased circuit speed, noise susceptibility and e...