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Method for an asynchronous FIFO featuring different-sized write and read data ports

IP.com Disclosure Number: IPCOM000010034D
Publication Date: 2002-Oct-09
Document File: 9 page(s) / 120K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for an asynchronous FIFO featuring different-sized write and read data ports. Benefits include improved functionality.

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Method for an asynchronous FIFO featuring different-sized write and read data ports

Disclosed is a method for an asynchronous FIFO featuring different-sized write and read data ports. Benefits include improved functionality.

Background

              An asynchronous FIFO is a type of first-in, first-out memory device. It is typically used for buffering data from one functional component to another to provide temporary storage when one component cannot submit or process the data as quickly as another component. An asynchronous FIFO enables the writer (the component submitting the data) and the reader (the component processing the data) to operate at different clock frequencies that are not synchronized to each other.

              Conventional designs have the limitation that the writer and reader must provide and retrieve data in exactly the same size quantity. Both writer and reader must process data items in 32-bit or 64-bit quantities. Such designs consist of a dual-ported RAM device (typically an SRAM) to store the data with one pointer indicating the next location to be read (the “read pointer”) and another pointer indicating the next location to be written (the “write pointer”).

              The write-side logic must have access to the read pointer to determine if the FIFO is full. The asynchronous FIFO must resynchronize the value of the read pointer from the reader’s clock to the writer’s clock. The value of the write pointer must be resynchronized from the writer’s clock to the reader’s clock. The read-side logic must have access to the write pointer to determine if the FIFO is empty. Resynchronization is typically done using a two-stage process. The value being resynchronized is first synchronized using flip-flops to one edge of the resynchronization clock, usually the falling edge. Then the value is synchronized to the other edge of the resynchronization clock, typically the rising edge, using flip-flops. This approach would appear to solve the problem, except that when using ordinary binary pointers, several bits may be changing at the same time. Due to varying propagation delays within ASICs, some bits may resynchronize to outdated values while other bits may resynchronize to the most current value. Another problem is that of metastability. If the input to a flip-flop changes too close to a clock edge, the flip-flop may malfunction and return an incorrect value.

              In conventional asynchronous FIFO designs, both pointers increment by only one after each read or write operation since the data is the same size exiting the FIFO as when entering the FIFO. Gray coding is a means of encoding binary numbers in such a way that only one bit changes when advancing from one number to the next. To avoid the problem of multiple bits changing simultaneously, many asynchronous FIFO designs convert their pointers to Gray code prior to resynchronizing them. An example illustrates how binary numbers change over time with how Gray-coded ...