Browse Prior Art Database

Method for a die stacking architecture for square and rectangular dies

IP.com Disclosure Number: IPCOM000010062D
Publication Date: 2002-Oct-16
Document File: 5 page(s) / 166K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a die stacking architecture for square and rectangular dies. Benefits include improved functionality and improved performance.

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Method for a die stacking architecture for square and rectangular dies

 

Disclosed is a method for a die stacking architecture for square and rectangular dies. Benefits include improved functionality and improved performance.

Background

      Package thickness is a factor that conventionally limits the stacking of dies in a package. Wire loop height and mold cap height add to the overall thickness of a stack package.

      The long loop length of wirebond stacking degrades the performance of stack packages.

 

              Conventional stacked package solutions include the following (see Figure 1):

•             Wire-bond stack die packages

•             Wire-bond flip-chip mixed stacks

•             Folded stacks

      Package thickness is conventionally addressed by the following methods:

•             Use a thinner die

•             Use a thinner substrate

•             Use a low loop wirebonding process

•             Use a thinner moldcap

      Dies are conventionally determined to be good by testing the package after stacking. Substandard dies result in yield loss because the entire stacked package must be scrapped.

Description

              The disclosed method is a technique to stack multiple dies for stack die packaging (see Figure 2, cross section). This method is an all flip-chip, low thickness stack architecture that utilizes a cavity substrate. The die is rotated 45 degrees relative to the cavity for a square die and 90 degrees for a rectangular die.

              A cavity is opened in the center of the substrate. The die is rotated in respect to the cavity. The overlapped area is flip-chip bonded. The next level has the same arrangement with the cavity aligned with the lower level die during stacking. The die protrudes into the cavity of the next level substrate, minimizing thickness. The next level die is again rotated and bonded to the substrate. This configuration can be repeated as many times vertically as required.

      For square chips, the stacking process is performed as follows (see Figure 3):

•             Lowest level (first stack level) substrate is a typical flip-chip package.

•             Second level substrate has a routed cavity in the center with the same dimension and orien...