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Method for a branched capacitor structure in the package for high-performance processor systems

IP.com Disclosure Number: IPCOM000010065D
Publication Date: 2002-Oct-16
Document File: 5 page(s) / 240K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a branched capacitor structure in the package for high-performance processor systems. Benefits include improved performance and improved functionality.

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Method for a branched capacitor structure in the package for high-performance processor systems

Disclosed is a method for a branched capacitor structure in the package for high-performance processor systems. Benefits include improved performance and improved functionality.

Background

        � � � � � The frequency of operation of a processor is set by the lower limit of the voltage in the voltage-tolerance window. As the voltage tolerance window around the nominal operating voltage is smaller, the VCC and frequency of operation are higher. The goal of package design is to minimize the voltage tolerance window and make it as small as possible around the nominal operating voltage by adding enough capacitance between the VCC and VSS power planes in the package.

        � � � � � The power (VCC) and ground (VSS) planes of the package are typically a parallel plate structure that is not efficiently decoupled results higher capacitance density. The parallel plate structure does not support improved packing design concepts.

        � � � � � The conventional state-of-the-art method of designing the metal layers in a package (see Figure 1) makes use of a parallel plate structure sandwiched by dielectric layers. A majority of the capacitance between the power (VCC) and ground (VSS) planes exist only in the vertical (Z) dimension. The geometry of the parallel plate structure is designed meeting the design rules set for its process technology. It provides the maximum capacitance density within the scope of substrate design rules.

        � � � � � For example, power pins are located in the north and south sides of the package and the power planes are constructed as a parallel plate structure. For a robust power delivery, the

power plane can be located above the VCC/VSS pin field with minimum antipads as this arrangement provides a low resistance connection. The power planes near the I/O signal field

utilize the branched plane construction to benefit from maximum capacitance density.


        � � � � � A requirement has been identified for CPUs to operate at multiple voltage domains because of its power-saving potential. The parallel plate structure does not support this requirement due to the increased noise coupling between the voltage rails because of having the I/O and core power planes adjacent to each other. To counter the noise, the package layer count could be increased to sandwich the power rails by VSS planes, which increases cost.

Description

        � � � � � The disclosed method is a branched capacitor structure integrated into a package. The structure increases the capacitance density by area efficiency.

        � � � � � The key elements of the method include:
•        � � � � Branched capacitor structure is used instead of the conventional metal layers alternating in the Z dimension only.

•        � � � � Branched capacitor structure alternate with VCC-VSS-VCC-VSS polarity in X/Y/Z dimensions (see Figure 2).
        � � � � � The disclosed method maximizes periphery to increase lateral electric field usage. It...