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Method to indicate possible loss of lockstep using debug and/or performance monitor resources

IP.com Disclosure Number: IPCOM000010109D
Publication Date: 2002-Oct-23
Document File: 2 page(s) / 26K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to indicate possible loss of lockstep using debug and/or performance monitor resources. Benefits include improved functionality.

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Method to indicate possible loss of lockstep using debug and/or performance monitor resources

Disclosed is a method to indicate possible loss of lockstep using debug and/or performance monitor resources. Benefits include improved functionality.

Background

        � � � � � Sixty-four bit processors contain error detection logic to recognize when single bit and multibit errors are detected by the processor. The machine check abort (MCA) architecture describes the detection capabilities of the processor including the instruction fetch resteer to a specific address: PALE. The 64-bit processor also has debug resources that monitor instruction fetch addresses. Additionally, this hardware can cause external events to occur because of recognizing an event, such as a particular instruction fetch. The external event may not be limited to the transitioning of external pins. Both the monitoring logic, error logic, and response logic can be configured in many different ways.

        � � � � � When the processor detects an error, the error often causes the processor to change its behavior. This change may cause two processors that are running in lockstep (such as, one processor checks the work done by another processor) to diverge. Logic monitoring the processors cannot determine which processor is correct and which processor detected the error until much after.

Description

        � � � � � The disclosed method programs the error detection/report resources of the processor to cause the processor to resteer instruction fetch to the PALE memory location. This memory location is an instruction cache miss. The debug resources are programmed to recognize the PALE address and trigger a response when an instruction fetch to the PALE address misses the instruction cache. Cache errors, which may be held off by the processor for a time before causing an instruction fetch to the PALE address, are also programmed to trigger a response. It transitions one or more of the background processing management (BPM) pins....