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Method for a lazy write-update policy for multiprocessor systems Disclosure Number: IPCOM000010118D
Publication Date: 2002-Oct-23
Document File: 9 page(s) / 332K

Publishing Venue

The Prior Art Database


Disclosed is a method for a lazy write-update policy for multiprocessor systems. Benefits include improved performance and improved functionality.

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Method for a lazy write-update policy for multiprocessor systems 


Disclosed is a method for a lazy write-update policy for multiprocessor systems. Benefits include improved performance and improved functionality.


              Relaxed consistency models improve the memory performance of 64-bit architecture multiprocessor systems by hiding much of the latency of memory operations. By relaxing the ordering of memory operations, processors do not stall as often for noncritical memory operations and enable the processor to reorder memory operations so that they improve performance. Many studies have shown that relaxing memory ordering improves performance.

              Sixty-four-bit processors use a consistency model similar to release consistency. The consistency model relaxes the ordering for remote processors of writes after reads (WARs), reads after writes (RAWs), and writes after writes (WAWs). Remote processors are not notified of reads except on cache misses. However, the reads are reordered with respect to writes in that the processor can perform a read before other processors receive notification of a previous write.

              In contrast, sequential consistency (SC) enforces a policy where all memory accesses must appear in the same order to all processors in a system. A read on one processor cannot appear to be performed before other processors detect a prior write. However, local reads and writes must be maintained in the order that they occur, except that reads may be reordered with respect to other reads (reads after reads or RARs). This consistency model restricts reordering of memory operations across acquires, releases, and memory fences.

              The disclosed method further exploits the potential improvement of relaxed write after write (WAW) ordering. This policy cannot be used in multiprocessor systems using 32-bit processors, because they use a relatively strong WAW ordering. In particular, 32-bit architecture enforces a policy that all writes must be performed in order with respect to each other.

              In many workloads, including most commercial workloads, a large amount of data is shared between the processors. Systems that use invalidation-based cache coherency protocols often suffer a large number of cache misses due to shared data. Only one cache can have a valid copy of a line that is written to, so a cache miss occurs every time that data is shared. Update-based coherency protocols attempt to solve this problem by sending updates of data written to by one processor to the other processors. While this policy removes cache misses for shared data, it requires a large amount of bandwidth and is impractical for most designs.

              Update-based protocols use a lot of bandwidth because the protocol requires that each processor send an update of the data to other processors soon after each write occurs. In contrast, invalidation-based protocols require much less bandwidth. When a processor performs a series o...