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Method for a high performance data transport interface

IP.com Disclosure Number: IPCOM000010119D
Publication Date: 2002-Oct-23
Document File: 5 page(s) / 127K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a high performance data transport interface. Benefits include improved performance, improved design flexibility, and improved ease of implementation.

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Method for a high performance data transport interface

Disclosed is a method for a high performance data transport interface. Benefits include improved performance, improved design flexibility, and improved ease of implementation.

Background

              The following acronyms are used in this disclosure:

•             CP: Control Processor, resides on each peripheral printed circuit board (PCB) to perform embedded data processing using a commercially available real time operating system (RTOS)

•             Host: Any commercially available operating system running a high-performance processor capable of supporting peripheral component interface (PCI) and compact peripheral component interface (cPCI) bus architecture

•             MF: Message Frame, packet of data that is transferred between the host and the CP and resides on the host random access memory (RAM)

•             MFO: Message Frame Offset, offset address aligned based on the size of the MF and points to a MF on the host RAM

              The Intelligent-IO Special Interest Group (I2O SIG) released a specification that defines the input/output (I/O) between a host and a board. The specification includes the following recommendations:

•             Complex stacks on both the host and the real-time operating system (RTOS)

•             Data transfer memory that is split between the board and the host, which prevents scalability due to a significant cost to increase board memory

•             Specific operating methods for both the host and RTOS, which causes adaptability to different architectures to be major issues

•             Data movement from the host to board memory that incurs PCI bus contention

•             Memory Frame Area (MFA) as a basic unit of transfer, which raises significant issues for 32/64-bit architectures

•             Data movement from both the host and the board

•             Host participation that is involved in all transfers

Description

              The disclosed method is data transport between a host central processing unit and PCI/cPCI boards. The host and CP communicate using a set of four first-in, first-out memory buffers (FIFOs). Two FIFOs are required for each direction. One FIFO acts as the post queue. The other acts as a free list queue (see Figure 1).

              The host and CP communicate by using MFOs as the basic communication blocks though the FIFOs.

              During initialization, the host allocates MFs on the main memory of the host processor and sends the MFOs to the two free list FIFOs. Because the host cannot access the free list FIFO for the host-to-board communication, the host uses the post queue to sen...