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Browse Prior Art Database

Back-Side Die Circuitry

IP.com Disclosure Number: IPCOM000010222D
Publication Date: 2002-Nov-06
Document File: 4 page(s) / 87K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that enables flip chips to be stacked on one another by using die back-side circuitization. Benefits include reduced inductance and enhanced thermal dissipation.

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Back-Side Die Circuitry

Disclosed is a method that enables flip chips to be stacked on one another by using die back-side circuitization. Benefits include reduced inductance and enhanced thermal dissipation.

Background

Currently, stacking flip chips on one another is not available. Figures 1 through 3 show the current state of the art.

General Description

The disclosed method combines existing packaging technologies in a novel way to enable enhanced functionality. Figures 4 and 5 show the details of the disclosed method:

 

  • Figure 4 shows a flip chip die with a WB die stacked on top.� The exposed back side of die improves thermal performance. A lower total Z height (due to elimination of WB on top of die and overmold) is needed to avoid WB damage. The disclosed method uses a bottom side wire bond application, and stacks the WB die upside down onto the flip chip die by screen printing on the back side of the die FC die (currently a non-functional surface).
  • Figure 5 shows a close up of the FC die with WB die stacked. Critical height dimensions are highlighted. The backside of the WB die is exposed to offer improved thermal performance. The WB length is also shorter offering reduced inductance.

Advantages

The following are advantages of the disclosed method:

 

  • Substrate stack-up reduction
  • Increased usable space by utilizing the back side of die
  • Increase flexibility by mixing flip chip dies for use with each other in a stacked configuration.
  • Improved thermal management by using the b...