Browse Prior Art Database

Method for an x80 DIMM

IP.com Disclosure Number: IPCOM000010225D
Publication Date: 2002-Nov-06
Document File: 3 page(s) / 80K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for an x80 DIMM. Benefits include improved functionality, improved reliability, improved performance, and improved design flexibility.

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Method for an x80 DIMM

Disclosed is a method for an x80 DIMM. Benefits include improved functionality, improved

reliability, improved performance, and improved design flexibility.

Background

        � � � � � A 64-bit error checking and correction (ECC) protected memory module with a 72-bit memory width (x72 DIMM) that implements a configurable data width memory controller (CDWMC) faces the problem of capacity loss. It can be up to 50% of the available memory when configured as a 32-bit system.

General description

        � � � � � The disclosed method is a DIMM that implements an 80-bit data bus (x80 DIMM) using a data mask for each data byte for a total of 10 data masks. The method enables two typical configurations:

•        � � � � 64-bit system with 8 bits of ECC (leaving 8 bits, or up to 10% total memory unused)

•        � � � � 2 lanes of 32-bit data each with 8 bits of ECC (leaving no memory unused)

        � � � � � For a system with a CDWMC, capacity loss can span from 0-10% (rather than 0-50%), offsetting the cost impact inherit in a CDWMC.

Advantages

        � � � � � Some implementations of the disclosed structure and method provide one or more of the following advantages:

•        � � � � Improved functionality due to enabling data bursting in memory architectures that use 32-bit and 64-bit busses while implementing ECC for single-bit correction

•        � � � � Improved reliability due to improved memory loss

•        � � � � Improved performance due to the use of the CDWMC

•        � � � � Improved design flexibility due to the use of the CDWMC

Detailed description

        � � � � � The x80 DIMM configuration decreases the possible memory capacity loss that is a result of a conventional CDWMC. This configuratio...