Browse Prior Art Database

Method for ATPG for scan designs with multiple clock domains and different scan styles of sequential memory elements

IP.com Disclosure Number: IPCOM000010252D
Publication Date: 2002-Nov-13
Document File: 5 page(s) / 105K

Publishing Venue

The IP.com Prior Art Database

Abstract

Method for automatic test pattern generation (ATPG) for scan designs with multiple clock domains and different scan styles of sequential memory elements. Benefits include an improved design environment and an improved test environment.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 50% of the total text.

Method for ATPG for scan designs with multiple clock domains and different scan styles of sequential memory elements

Method for automatic test pattern generation (ATPG) for scan designs with multiple clock domains and different scan styles of sequential memory elements. Benefits include an improved design environment and an improved test environment.

General description

              The disclosed method resolves the issue of testing complex sequential register transfer logic (RTL) design into a much simpler problem, that of Automatic Test Pattern Generation (ATPG) for combinational logic testing. It is similar to the conventional level-sensitive scan methodology (LSSD). For debug and device bring-up purpose (DFD), multiplex flip-flop style (MUX-FF) sequential elements are implemented.

              Two different scan styles coexist in the disclosed design. A brief description and its salient features include:

•             Test mode operation only for manufacturing defect screening.
•             Lower frequency operation during data load/unload shifting
•             Level sensitive (rather than edge triggered) scan clocks

•             MUX-FF for device debug and bring-up purposes
•             Data capture in functional mode at functional frequency
•             MUX-FFs that are chained together (DFD scan chain)
•             Captured data that are serially shifted out at operational frequency

Advantages

              The disclosed method provides advantages, including:

•             Improved test environment due to 100% coverage for ATPG

•             Improved design environment due to resolving the coexistence of multiclock domains, and multiscan styles within the same RTL

Detailed description

              The disclose method is automatic test pattern generation (ATPG) for scan designs with multiple clock domains and different scan styles of sequential memory elements.

              Only one of the two clock domains can be active at any giving time but not both simultaneously. This approach prevents data propagation between different clock domains while in active mode. This strict enforcement resolves the problem of data corruptions and race conditions in a multi-clocks design environment. As a result, the design complexity is vastly simplified. From scan ATPG perspectives, the disclosed design includes the following distinct clock domains:

•             T-scan clock domain: Consists of A-clock, B-clock, operating at slower frequency, and in the scan mode

•             DFD clock domain: A derivative of the functional clock. Its operation consisting of capturing data into the debug latches (in functional mode, at normal operation frequency), and then shifting the captured data out serially

•             Functional clock domain

              Data propagati...