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Method to reduce the area and increase the speed of a highly ported register file

IP.com Disclosure Number: IPCOM000010255D
Publication Date: 2002-Nov-13
Document File: 7 page(s) / 107K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to reduce the area and increase the speed of a highly ported register file. Benefits include improved performance.

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Method to reduce the area and increase the speed of a highly ported register file

Disclosed is a method to reduce the area and increase the speed of a highly ported register file. Benefits include improved performance.

Background

        � � � � � A register file is one of the key data-path components in a modern microprocessor. It serves as the highest level of memory within the memory hierarchy. A register file communicates the results among computations. The access time of the register file affects the processor performance. As instruction issue widths increase, the number of ports for a register file also grows. As access port and size increase, the access time degrades, and the power consumption of the register files increases. The result is a requirement for an alternative design to the conventional register file.

        � � � � � A conventional memory structure, such as a register file, is typically organized into a two-dimensional array with bit lines and word lines orthogonal to each other. Word lines are used to select a particular row of this array. Column bit lines are used to transfer data in and out of the array. As technology scales, wiring delays are becoming a more significant contributor to the overall delay of a functional block. Using fewer word lines makes the height of a column shorter and improves performance.

        � � � � � Device leakage current poses many challenges to memory array design. If a particular column has one cell storing the opposite data value from the rest of the cells, reading that cell may be problematic because the off current of the access device must compete withthe sum of all the leakage current. If the sum of all leakage current is comparable in value with the on current of data cell being read, then we may read out a wrong result. One of the solutions is to reduce the number of cells on a particular bit-line by building a hierarchical bit-line structure. Local bit lines have a limited number of cells on them and several local bit lines are combined to access a global bit line vertically. This solution tends to reduce area density due to reduce array efficiency.

        � � � � � Access wires are the main contributor to the area of multi-ported register cell. One conventional design is a register cell with 2-read and 2-write ports (see Figure 1). The register cell has 4 bit lines and 4 word lines per register bit because this particular implementation uses one bit-line and one word-line for each port. Other conventional implementations require two bit lines per port. If the number of ports is larger, then the number of wires bound the cell area.

�         � � � � The area of a highly ported register file cell is proportional to the square of the number of ports, because each port needs a word-line to select the cell for access and a bit-line to enable data to transfer. The access speed is proportional to the size of register file. Shorter bit lines means lower bit line capacitance and faster rise/fall time.

General description

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