Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Folded Stacked Flex Tape Passive Package

IP.com Disclosure Number: IPCOM000010329D
Publication Date: 2002-Nov-20
Document File: 3 page(s) / 62K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that incorporates passives into products with folded stacked flex tape technology. Benefits include increasing board space.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 50% of the total text.

 

Folded Stacked Flex Tape Passive Package

Disclosed is a method that incorporates passives into products with folded stacked flex tape technology. Benefits include increasing board space.

Background

Currently, enclosures of passives into the package are:� 1) done either through placement outside and peripheral to the package, 2) beside the chip on the substrate in multi-chip modules, 3) underneath the package or 4) incorporated into the die itself.� All of these methods have their individual advantages and disadvantages.

Placement outside of package on the actual circuit board has the advantage of ease of convertibility at the OEM takes up board space that could be used for other components.� Also, with today’s movement to increased functionality in reduced size, i.e. PDA’s, multifunction cell phones, form factor of the above method is limited.� Another method currently used is to have a large substrate and the passive components are placed on the substrate as a miniature printed circuit board.� This reduces the OEM convertibility but allows for decreased board routing and increased signal integrity.� However this also takes board space also and is detrimental as for the reasons observed above.� Incorporation of passive components directly into the die is also used today in the industry.� While in all cases this is optimum, the cost of this process at this point is prohibitive and it also increases the die footprint.

Passives have also been placed on top of the die with some non-CPU programs and attachment below the die of passives is a BKM for CPU practices.� However as we look at incorporation of these we are limited by Z-height thickness using conventional B.T. or FR4 technology.� The indicated technology currently has a minimum height of about 50-60...