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Method for selective register file reading for load and store operations in an AGU

IP.com Disclosure Number: IPCOM000010335D
Publication Date: 2002-Nov-20
Document File: 4 page(s) / 82K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for selective register file reading for load and store operations in an address generation unit (AGU). Benefits include improved power performance.

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Method for selective register file reading for load and store operations in an AGU

Disclosed is a method for selective register file reading for load and store operations in an address generation unit (AGU). Benefits include improved power performance.

Background

              Several terms are used in this disclosure, including:

RS – Reservation station, unit used by the micro-architecture to send commands to the execution units. The RS implements the core of the out-of-order algorithm. The RS schedules commands when their operands are ready rather than in the order they were read by the processor.

AGU – Address generation unit, calculates linear and effective addresses and checks the validity of memory accesses. The AGU also holds the segment register file (see Figure 1).

Linear address – Address used to access the caches and the TLB. After page mapping, it is converted to a physical address. The linear address is calculated by:

Linear_addr = Segment_base + Base_reg + Index_reg * Scale + Displacement

Effective address – Offset into the segment space. The effective address is used for checking the validity of the access operation and is compared to the segment limit value.

Effective_addr = Base_reg + Index_reg * Scale + Displacement

Fig. 1

Segment register read – Operation performed by the AGU when the content of a segment register is required. The RS supplies a 5-bit value of segment register ID, and the AGU performs read to the indexed register. Segment register read is a frequent event that occurs for every memory load or store operations.

Segment register – Structure defined in the architecture to implement the segmented memory model. Each segment register contains a 32-bit segment base address, a 20-bit segment limit, and several attributes, such as the access rights to the segment and the segment granularity.

              Load and store operations performed by the AGU require reading the segment register file. In its first stage, the AGU performs the segment read. Then the AGU performs addition with the other values to generate the linear address. The operation of segment register file read is power consuming because it is 80-bit wide dynamic memory that is tuned for extreme timing requirements.

              The conventional method is comprised of the following steps (see Figure 2):

1.           The address (segment register ID) is received.

2.           The address is decoded.
3.           The bit line is set.
4.           The read value is latched in the output latch.

General description

              The disclosed method is selective register file reading for load and store operations in an address generation unit (AGU). The main feature is the selective segment read mechanism. This p...