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Method for pulse scheduling to reduce the complexity of high-bandwidth selection logic

IP.com Disclosure Number: IPCOM000010336D
Publication Date: 2002-Nov-20
Document File: 2 page(s) / 44K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for pulse scheduling to reduce the complexity of high-bandwidth selection logic. Benefits include improved performance.

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Method for pulse scheduling to reduce the complexity of high-bandwidth selection logic

Disclosed is a method for pulse scheduling to reduce the complexity of high-bandwidth selection logic. Benefits include improved performance.

Background

        � � � � � Conventional schedulers contain a critical timing path in the select-to-ready loop. It is comprised of logic to examine the source-ready bits, the select logic in the scheduler, and the ready request update. The source-ready bits generate the ready request. The ready-request update turns off the instructions-ready bit after it is selected. If the ready request is not turned off during the select cycle, the scheduler may select that instruction again in the next cycle. Selecting an instruction several times leads to a loss in performance and, potentially, a functional failure. This critical logic path can easily be the limit on the clock frequency or similarly limit the scheduler size at frequency.

Description

        � � � � � The disclosed method modifies the ready logic of a typical out-of-order scheduler (see Figure 1). A block of logic is added between the ready signal and the scheduler/picker. This logic disables the ready signal for some number of cycles, designated as n, independent of selection (see Figure 2). The select signal can be pipelined without causing the scheduler to select the same instruction multiple times or speculatively remove the entry from the scheduler. The implementation of this logic block is straight forward...