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Mechanism for an Efficient Multi-Chooser Scheduler for Single Instruction Windows

IP.com Disclosure Number: IPCOM000010337D
Publication Date: 2002-Nov-20
Document File: 2 page(s) / 31K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that enables a wider scheduler for a given instruction scheduling window. Benefits include wider schedulers at higher frequencies.

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Mechanism for an Efficient Multi-Chooser Scheduler for Single Instruction Windows

Disclosed is a method that enables a wider scheduler for a given instruction scheduling window. Benefits include wider schedulers at higher frequencies.

Background

Traditional schedulers begin with the “oldest” instructions first, from a set of ready instructions (see Figure 1). However, the complexity of choosing multiple instructions from the same instruction window grows as a function of chooser width. The wider the scheduler, the more� complex are the linear selection dependencies; cycle time is also increased for the scheduler.

General Description

The disclosed method adds a reverse order chooser (i.e. “newest” first) to increase scheduler width and simplify the choosing process. The disclosed method improves the critical portion of the chooser dependency chain of prior art choosers. Figure 2 shows an example of the disclosed method; while the 3rd chooser in this example still requires a check against the 1st and 2nd choices, the 3rd chooser invalidates its choice in case of a match, in order to avoid the same instruction being chosen multiple times.

The advantage of using a reverse scheduler that can do match invalidate is that the match invalidate can be pipelined (for high frequency) with no loss in performance. In contrast, two or more schedulers searching in the same order will require more complexity and latency for each additional scheduler added. In that case, the performan...