Browse Prior Art Database

Nonvolatile CAM (Content-Addressable Memory) cell using MRAM (Magnetic RAM) memory elements

IP.com Disclosure Number: IPCOM000010378D
Original Publication Date: 2002-Nov-22
Included in the Prior Art Database: 2002-Nov-22
Document File: 5 page(s) / 38K

Publishing Venue

IBM

Abstract

Disclosed is nonvolatile content-addressable memory (CAM) cell that has high-speed, low-power, and soft-error immune characteristics. The cell uses magnetic tunnel junction (MTJ) memory elements for non-volatility that are being used in magnetic or magneto-resistive memories (MRAM).

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 38% of the total text.

Page 1 of 5

  Nonvolatile CAM (Content-Addressable Memory) cell using MRAM (Magnetic RAM) memory elements

   Disclosed is nonvolatile content-addressable memory (CAM) cell that has high-speed, low-power, and soft-error immune characteristics. The cell uses magnetic tunnel junction (MTJ) memory elements for non-volatility that are being used in magnetic or magneto-resistive memories (MRAM).

   Recently it is recognized that the static memory cell like ones used in conventional CAMs has problems of high soft error rate (SER) because of smaller device size, and lower power-supply voltage (VDD) and threshold voltages (Vt). Also with the lower Vt in recent advanced technologies the standby current becomes larger and larger due to the sub-threshold leakage current of the MOSFETs.

   A nonvolatile CAM cell could drastically reduce the standby power of the CAM through shutting off the power supply to the cells. MRAM cells have non-volatility and high immunity to soft errors, but it cannot be used for logical comparison in CAM cells because MRAM cells do not have big enough output signals. Thus new circuits are required to incorporate non-volatility of MRAM's memory element in CAM cells.

   Fig.1 shows an embodiment using CMOS circuits of the new CAM cell concept with MTJ memory elements.

BL BL

WL

T1

T2

T3

T4

SNT SNC

T5 T6

MTJ MTJ

Write WL

DT

T7 T8

Word Match Line

Write BL Write BL

T9

Fig. 1

1

[This page contains 3 pictures or other non-text objects]

Page 2 of 5

Example of timing chart

Simulation results

BL BL

Voltage(V)

   FETs T1 and T2 make an inverter, and T3 and T4 make the other inverter. T5 and T6 are access transistors for true side and complement side respectively. T7 and T8 make the logical compare circuit and T9 is the word match line driver. SNT and SNC are the storage nodes for true side and complement side respectively. The write bit line (write BL), write bit line bar (write /BL) and write word line (write WL) are used for write operation. The bit line (BL) and bit line bar (/BL) are used for read operation and search operation. The word line (WL) is used for read operation. The data transfer line (DT) and word line (WL) are used to transfer the data from the MTJ pair to the cross-coupled inverter pair.

   Data writing is done to the MTJ elements and the written datum is not reflected to the storage nodes SNT and SNC just by writing to the MTJ elements. The information stored in the pair of the MTJ elements is, therefore, transferred to the cross-coupled inverters in the memory cell before the information is needed for search operation or read operation. The data transfer is done by making use of the amplifying and latching functions of the cross-coupled inverters. The data transfer can also take place during the write operation.

   An example of the control of the signals for the data transfer is shown in Fig. 2(a). Fig. 2(b) shows simulation results of the data transfer from the MTJ pair to the cross-coupled inverters. It is assumed in these charts that the...