Browse Prior Art Database

Compare-Port Disbaling For Power Reduction

IP.com Disclosure Number: IPCOM000010388D
Original Publication Date: 2002-Nov-22
Included in the Prior Art Database: 2002-Nov-22
Document File: 5 page(s) / 89K

Publishing Venue

IBM

Abstract

Power Management becomes more and more important in modern high frequency designs as for portable equipment. Disabling complete units or arrays are a general scheme for reducing the power, but more granular concepts are necessary. Disclosed is a scheme to disable the compare function of individual entries in a Content-Addressable-Memory (CAM) after a match in order to reduce the overall power consumption while the arrays stays active. Two implementations are shown, one for minimum area and one for maximum performance.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 34% of the total text.

Page 1 of 5

Compare-Port Disbaling For Power Reduction

0 Abstract

Disclosed is a scheme to disable the compare function of individual entries in a Content-Addressable-Memory (CAM) after a match in order to reduce the overall power consumption. Two implementations are shown, one for minimum area and one for maximum performance.

1 Introduction

    Power management becomes more and more important in modern high frequency designs as well as for portable equipment. Disabling complete arrays is a general scheme for reducing the power consumption, but more granular concepts are necessary. The ultimate goal is to minimize power consumption while the array is still active.

    Conceptionally CAM's are used to detect entries to read data from or write data into and/or set status bits. The decode mechanism is a compare of a tag address with all entries of the memory array in parallel. In many applications only one match can occur during the lifetime of an entry. An example of such an application is the CAM that calculates the validity of the operand data. Once the operand data has become valid it will stay valid until the entry is removed from the reservation station.

    In such cases the CAM cell of an entry can be disabled till the entry is loaded with a new instruction thereby reducing overall power consumption and noise generation on an entry by entry basis.

2 CAM Structure

    A CAM array (Fig. 1) is characterized by the number of tag entries 'j' ;, number of bits 'i' of each tag and the number of tag input ports 'k'. Each entry contains a tag (with bit width 'i') to which the 'k' tags (each with bitwidth 'i') of the input ports are compared to. Hence for the total CAM array k times j tag compares are done in parallel during each cycle and compute the resulting match signals "match(0..j-1,0..k-1)" . Thereby each match(l,m) signal, with l=0...j-1 and m=0...k-1, indicates if the tag data of entry l matches the tag data on the input port m (or not).

    Each tag compare cell has an integrated compare function for a bitwise compare. A match across a word is the 'and-ing' of all matches of the individual bits. Alternatively also the mismatch can be detected by ' or-ing' the mismatches of individual bits across the word.

    In a dynamic circuit scheme the 'or' is the fastest possible implementation. All cells are connected in parallel via a pull-down device to the match line. This match line is precharged to VDD. The compare port of a cell is connected to the pull-down device. When a mismatch in at least one cell occurs the pull-down device is activated and the match line discharged to GND thereby detecting the miss-compare. The result is stored in a valid bit to be used for further processing.

    Fig 2 shows the compare port of the CAM cell in more detail (read and write not shown). The storing node is shown as a feedback latch with the nodes T & C, holding the true and complement value. The inverter It & Ic connect the cell to the compare port (or several ports in case of a mu...