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Method for the horizontal chopping of a large on-chip cache

IP.com Disclosure Number: IPCOM000010420D
Publication Date: 2002-Nov-27
Document File: 5 page(s) / 108K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for the horizontal chopping of a large on-chip cache. Benefits include improved functionality and improved ease of design/implementation.

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Method for the horizontal chopping of a large on-chip cache

Disclosed is a method for the horizontal chopping of a large on-chip cache. Benefits include improved functionality and improved ease of design/implementation.

Background

        � � � � � Choppability is a design requirement for on-chip large caches in addition to the conventional high density, low power, and high clock frequency constraints. For example, if a microprocessor is designed with a 1-MB on-die cache, the cache size may be reduced (chopped) to 512 KB to deliver a cheaper (value) stepping of the processor. A choppable cache should address the requirements of different products (or market segments) with little layout/redesign effort and no compromise of clock frequency or power efficiency. This variability in cache size poses a significant challenge to cache organization and performance.

        � � � � � With conventional implementations, the placement of the cache on the right (or left) side of the die enabled choppability (see Figure 1). A typical choppable cache has two banks each storing half of the data. A number of bits, designated as N, are read from or written to either bank based on a select signal. The size of the cache can be cut by two by taking out the bank close to the edge of the die, decreasing the size of the chip and sliding the input/output (I/O) pads inwards. The cache interface logic (IL) and the status arrays (SAs) are not affected, as they are placed parallel to the chop line. This vertical chopping entails minimal layout and design effort.

        � � � � � The cache controls communication to/from the cache. The SAs store information about the cache lines.

        � � � � � Cache cannot always be placed on the right or left side of the die due to surface area layout constraints. For example, the cache scheme illustrated in Figure 1 can be placed at the bottom of the die (see Figure 2). The shapes of both the cache and the core are changed to produce a feasible aspect ratio. The cache line remains N-bits wide. However, half of the bits are directed to each bank. If the cache is chopped using the vertical method, two issues occur. No area is saved as the die size is limited by the processor core logic. The line width is reduced from N to N/2, decreasing the cache bandwidth and overall processor performance. The result is a requirement for another cache organization that enables efficient horizontal chopping.

        � � � � � An alternative would be to redesign the processor core to match the cache. This approach can result in an unfeasible die aspect ratio and entails a large layout and redesign effort, which is a violation of a basic requirement of choppability.

General description

        � � � � � The disclosed met...