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Method for a Pcache, PTLB, and P/D/I unified implementation as an amendment to existing architectures with ISA additions

IP.com Disclosure Number: IPCOM000010421D
Publication Date: 2002-Nov-27
Document File: 9 page(s) / 160K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a Pcache, PTLB, and P/D/I unified implementation as an amendment to existing architectures with instruction set architecture (ISA) additions. Benefits include improved functionality, improved performance, and improved reliability.

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Method for a Pcache, PTLB, and P/D/I unified implementation as an amendment to existing architectures with ISA additions

Disclosed is a method for a Pcache, PTLB, and P/D/I unified implementation as an amendment to existing architectures with instruction set architecture (ISA) additions. Benefits include improved functionality, improved performance, and improved reliability.

Background

              Several terms and abbreviations are used below, including:

•             BTB: Branch target buffer

•             D: Data

•             Dcache: Data cache

•             I: Instruction

•             Icache: Instruction cache

•             ISA: Instruction set architecture

•             LRU: Least recently used

•             NOP: No operation performed

•             P: Pointer

•             Pcache: Pointer cache, one of the first-level memory hierarchy encountered when an address leaves the CPU. This particular cache applies only to pointers to data, objects, or other pointer-entities. The Pcache works as an integral part of the microarchitecture and is used in tandem with data, trace, and/or instruction cache (Icache) at the first level from the processor in conjunction with the instruction pipeline and PTLB.

•             PTLB: Pointer-based transaction look-aside buffer, which holds a tag to portions of the virtual address and the data portion holds a method to fully identify the Pcache entry or the physical page frame number if a Pcache miss occurs. To address security, a protection bit, valid bit, and dirty bit apply to ensure access of pointer-based data is secure, which is operating system implementation specific.

General description

              The disclosed method is a Pcache, PTLB, and P/D/I unified implementation as an amendment to existing architectures with ISA additions for improved dynamic runtime performance at the microarchitectural level. The method adds a first-level Pcache that contains full logical 32-bit addresses, which occur while processing the instruction stream. This change can also be adapted to a 64-bit address schema. A PTLB, which is fully associative, maps the current instruction pipeline’s pointer data criteria.

              The Pcache can be one of several sizes, including:

•             16-Way set associative mapping with 162 entries for the cache

•             32-Way set associate mapping with a 322 size for the cache

•             Pointer-sized cache line with multiples of 1024k lines

•             Some other size that optimally represents the mapping as proven by simulation that may not be symmetrical

Advantages

              The disclosed method provides advantages, including:

•             Improved functionality due to the added movpc, movpcf, and movpccmp instructions

•             Improved performance due to microarchitecture and ISA amendments

•             Improved performance due to Pcache-enabled prefetching hints

•             Improved performance due to executing instructions as NOPs when all required information is available in cache

•             Impr...