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SLEW RATE ENHANCEMENT IN HIGH VOLTAGE AMPLIFIERS

IP.com Disclosure Number: IPCOM000010424D
Publication Date: 2002-Nov-28
Document File: 4 page(s) / 243K

Publishing Venue

The IP.com Prior Art Database

Abstract

ID609704

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Page 1 of 4

1 DESCRIPTION

OF INVENTION DISCLOSURE: SLEW RATE ENHANCEMENT IN HIGH

VOLTAGE AMPLIFIERS

The traditional simplified circuit diagram of today's high voltage amplifiers is shown in Figure 1:

VCC 1

R2

R1

C1

-0V OUT

Q1

D1

1Q ~

VCC

Z Fdbck

< Q driver

ZJnp

V1

Figure

1 Traditional simplified circuit

of high voltage amplifier with boost capacitor

The traditional circuit

of

the high voltage amplifier with boost capacitor

is drawn

in Figure

1.

In this Voltage source VI drives the input of an

error amplifier. This amplifier is build around driver transistor Q_driver, an network Z_Inp

and

a feedback network Z_Fdbck; the collector

of transistor Q_driver drives

the emitter

Q2.

The collector resistor

of

Q2

is R2.

The load

at V_OUT

is often only

a capacitor.

The power dissipation

of

Q2

and R2

is mainly determined

by

the specification

for

the desired positive slew rate

at

the

output. Due to the

capacitive load on V_OUT the maximum emitter current of Ql determines positive slew rate. The maximum emitter current of Ql is

limited due to the

base Ql. The

for Ql is supplied

via resistors Rl

and R2 from

the supply VCC_1.

The implementation

of Cl

and maintains

a constant current through

Rl which

is

not affected

by

the actual output voltage

but only

by

the average voltage; otherwise

the current through Rl would decrease with increasing output voltage and make the slew rate even less at higher voltages. However the current through Rl is

used to supply three parts:

1 Base

current Ql 2 Discharge

current collector - base capacitor Ql 3 Charge

  current collector - base capacitor Q2 In order to increase the maximum positive slew rate at V_OUT while maintaining equal power consumption from VCC_1, there are three ways:

* Increase

die current gain

of

Ql: this would decrease

the base

of

Ql

and leave more

for

the collector

- base capacitors of Ql and Q2

1

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Page 2 of 4

* Decrease

the collector - base capacitor of Ql / Q2

(Ql and Q2 are

often the same type!): this would allow a faster rise of the

voltage at the

    base Ql. Since the collector - base capacitor

of

Ql parasitic part inside transistor housing (plus some additional external capacitance due

to

pcb tracks etc.) this

is

no alternative. Increasing

the current gain

of

Ql

is possible by using

a darlington configuration for this position. This however increases the total cost of the

   design significantly since price one high voltage transistor Ql represents

40

to total cost

of

one amplifier

as shown

in Figure 1.

A more cost effective solution is therefor

to connect

the darlington configuration

as presented

in

the next Figure

2.

VCC 1 p ~

R2

R1

Q3

D2

-M-

Q1

D1

-OV OUT

VCC 2

C1

Z Fdbck

Q2

Q driver

---£-

"I

ZJnp

Q1

Figure

2 Same circuit

as previous

but with

low voltage darlington

for

In Figure 2 the

collector of Q3 is not

connected to VCC_1 as in a

normal darlington configuration for Ql

would be done, but instead

to

the interconnection point

of Cl

/ Rl R2.

By

the prop...