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POWER DEVICE WITH INTEGRATED POLYSILICON DIODES AND LOW ON-RESISTANCE

IP.com Disclosure Number: IPCOM000010439D
Publication Date: 2002-Dec-02
Document File: 8 page(s) / 81K

Publishing Venue

The IP.com Prior Art Database

Abstract

A structure and method of forming a semiconductor power device having ESD, over-temperature and over-voltage protection schemes and a temperature compensated sustaining voltage is provided by integrating a plurality of temperature compensated voltage reference diodes. The diodes protect the device by clamping the device’s sustaining voltages to the total avalanche voltage of the diode. Historically, providing ESD protection for high density power MOSFET’s operating in the 8 to 500 volt range and having low on resistance (Rdson) has been difficult. Complicating factors include the use of self aligned implants and contacts as well as the many complicated and expensive process steps required to realize the finished device. Furthermore, complicated interconnections to gate and source are required which add further cost and processing steps. Prior methods primarily utilize non-self aligned power MOSFET technologies which suffer from less than optimal electrical performance and high cost. Therefore, it would be advantageous to provide a structure and method of integrating polysilicon diodes with a power MOSFET device. This will in turn allow for integrating ESD protection, temperature sensing, over-temperature protection and over-voltage protection features. Keywords ESD, MOSFET, POWER DEVICE, SELF-ALIGNED, POLY DIODE, TEMPERATURE SENSING, OVER-VOLTAGE PROTECTION

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POWER DEVICE WITH INTEGRATED POLYSILICON DIODES

AND LOW ON-RESISTANCE

Abstract

A structure and method of forming a semiconductor power device having ESD, over-temperature and over-voltage protection schemes and a temperature compensated sustaining voltage is provided by integrating a plurality of temperature compensated voltage reference diodes.� The diodes protect the device by clamping the device’s sustaining voltages to the total avalanche voltage of the diode.�

        � � � � Historically, providing ESD protection for high density power MOSFET’s operating in the 8 to 500 volt range and having low on resistance (Rdson) has been difficult.� Complicating factors include the use of self aligned implants and contacts as well as the many complicated and expensive process steps required to realize the finished device.� Furthermore, complicated interconnections to gate and source are required which add further cost and processing steps.� Prior methods primarily utilize non-self aligned power MOSFET technologies which suffer from less than optimal electrical performance and high cost.�

        � � � � Therefore, it would be advantageous to provide a structure and method of integrating polysilicon diodes with a power MOSFET device. This will in turn allow for integrating ESD protection, temperature sensing, over-temperature protection and over-voltage protection features.

Keywords

ESD, MOSFET, POWER DEVICE, SELF-ALIGNED, POLY DIODE,

TEMPERATURE SENSING, OVER-VOLTAGE PROTECTION

A cross-section of a first embodiment of the device structure is shown below (FIG. 1).

 
 

Poly Diodes (1st poly layer)

 
 

P+

 

Oxide 1

 

Oxide 2

 

Oxide 3

 

Spacer

 

Nitride

 

Poly

 

Field Oxide

 

Source Metal

 

Gate Metal

 

N+

 

P-

 

N+

 

P-

 

N+

 

PHV

 

N- EPI

 

N+ Substrate

 

ONO Stack

 

N+ Poly:Gate Poly (2nd Poly layer)

 
 

The main process steps to fabricate the above device are:

  1. Initial oxidation, active area definition.
  2. Sacrificial oxide, 1st poly deposition (for diode).
  3. Blanket implant 1st poly with boron.
  4. 1st poly mask, poly etch, resist strip.
  5. Sac oxide etch.
  6. Gate oxidation, poly deposition, poly implant (N+), ONO formation.
  7. 2nd poly mask.
  8. ONO etch, resist strip, poly etch.� Clear ONO and 2nd poly over diode regions.
  9. PHV implant and drive.
  10. N+ block PR, source implant. Also patterns and implants poly diodes on 1st poly layer.
  11. Spacer TEOS deposition, spacer mask, spacer etch. Leave oxide on top of diodes, except where contact is required.
  12. P+ implant. Also goes into N+ contacts of poly diode, but not enough to degrade diode performance.
  13. Conatct PR and etch.
  14. N+ drain ring implant.� Also implants N+ poly gate and N+ poly diode poly contacts.
  15. Contact PR strip.
  16. N+ and P+ anneal.
  17. Front metal, metal PR, and metal etch.
  18. Backgrind, backmetal.

In a second embodiment, the Poly layer for diode can also be deposited after gate poly and ONO deposition. The stack of poly, ONO, poly can then be patterned with one mask.� Poly diodes will now be on top of the poly/ONO stack.� The diode poly layer can then be etched off from the MOSFET regions...