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HIGH-END MULTI MODE VOLTAGE CONVERTER

IP.com Disclosure Number: IPCOM000010669D
Publication Date: 2003-Jan-08

Publishing Venue

The IP.com Prior Art Database

Abstract

Keywords POWER MANAGEMENT, ANALOG, DIGITAL, CURRENT CONTROL, VOLTAGE CONTROL, CLOCK, OPERATIONAL AMPLIFIER

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HIGH-END MULTI MODE VOLTAGE CONVERTER

Keywords

POWER MANAGEMENT, ANALOG, DIGITAL, CURRENT CONTROL, VOLTAGE CONTROL, CLOCK, OPERATIONAL AMPLIFIER

Background

Precise, low cost control of the operating voltage and/or current of voltage regulators embedded in cellular phone power supply units using either a digital or an analog drive is a highly desirable feature and commercially lucrative.  Today’s DC/DC converters typically operate using either voltage or current control mode, or by adding additional components; a selectable mode of operation whereby depending upon load conditions either voltage or current control is affected.  One problem of these selectable mode types of converters is that separate digital and analog components are required to provide the selectable mode operation, which increases cost and complexity.

Thus, a significant commercial advantage would be gained by producing a precise, low cost, low component count voltage converter.

Prior Art

First, several circuits and methods of prior art will be shown and discussed to better illustrate problems that are overcome by the invention of the present application.

The simplified schematic diagram given figure 1 describes an analog control circuit (voltage loop control mode) of the prior art.  The integrated circuit provides the clock signal, which is gated by U6A and applied to the totem pole Q1/Q3.  The buffered output of these two MOS drives the external power MOSFET Q5, which is used to charge inductor L1.  The external Schottky diode D1 provides the boost operating mode to charge capacitor C1 connected across the load.  The resistor network R3/R6, associated with the internal operational amplifier U1, yields the feedback voltage regulation.  The integrated band gap gives the voltage reference used by the analog functions.  In order to prevent damage to the circuit, the Q5 current sensed by the external resistor R5 is derived to the comparator U2 which, in turn, disable the clock applied to the totem pole driver.  The latch is reset upon the next positive going transient of the clock signal. 

One problem with this approach is that operation is limited to boost mode, thus cannot cope with full input voltage range as required by a battery operated system.  Also note the number of components required, that is, the power MOSFET is external to the controller chip, the Schottky diode is external to the controller chip, and the short circuit current sense is external to the chip and monitors the current flowing into the MOSFET Q5 only.

The simplified schematic diagram given figure 2 describes a second prior art approach, such as analog control of a current loop system.  The integrated circuit provides the clock signal, which is gated by U6B and applied to the totem pole Q2/Q4. The buffered output of these two MOS drives the external power MOSFET Q6, which is used to charge inductor L2.  The external Schottky diode D2 provides the boost operating mode to charge capacitor C2 connected acr...