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Method for substrate cavity and interconnect to facilitate package stacking

IP.com Disclosure Number: IPCOM000010681D
Publication Date: 2003-Jan-08
Document File: 2 page(s) / 47K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for substrate cavity and interconnect to facilitate package stacking. Benefits include improved performance, and improved ease of manufacturing.

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Method for substrate cavity and interconnect to facilitate package stacking

Disclosed is a method for substrate cavity and interconnect to facilitate package stacking.� Benefits include improved performance, and improved ease of manufacturing.

Background

        � � � � � Identified requirements include stacking very expensive logic die in 4+ die stack configurations (see Figure 1). Given yield and die defect issues, one bad die can cause an entire package with 4+ die to be scrapped. Conventionally, all die including logic are stacked in a single package using existing stack chip scale package (SCSP) packaging technology.

        � � � � � The proposed stacked package design separates the logic die into a separate package. It is stacked using an interposer that is attached as a separate substrate in a single-unit format.

General description

        � � � � � The disclosed method is a substrate cavity and interconnect to facilitate package stacking.

A low-cost substrate with an interposer facilitates the ability to interconnect shared signals to another package by stacking packages vertically.

        � � � � � The key elements of the method include:

•        � � � � Creation of a cavity build-up layer on a substrate

•        � � � � Build-up layer that is standard epoxy resin/woven glass-cloth core material or polyimide-based material that is one layer

•        � � � � Cavity build-up design that is performed in panel format at the substrate supplier to enable a lower total-cost substitute to the interposer design while...