Browse Prior Art Database

Multi-Instance Programmable State-Machine

IP.com Disclosure Number: IPCOM000010714D
Original Publication Date: 2003-Jan-14
Included in the Prior Art Database: 2003-Jan-14
Document File: 4 page(s) / 71K

Publishing Venue

IBM

Abstract

Programmable logic structures only start to appear as cores in System-On-Chip designs. They have many applications there and the need for multi-instance protocol processing is not yet ubiquous. For the use of programmable logic structures to implement protocol state machines, a subset of the Flip-Flops is enhanced to allow automatic state exchange using a separate table. The enable inputs of these "persistent registers" are observed to avoid unnecessary store-backs of unchanged states to the table. Routing resources are enhanced by dedicated wrap-around wires to create a pipe-topology which is more useful for the implementation of state machines than current art meshes.

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Multi-Instance Programmable State -Machine

  A lot of services in network components or network attached devices are stream oriented. They include the execution of communication protocols. Examples are TCP, Fibre Channel over IP, iSCSI, Header Compression. In such a device, frequently many streams are handled at the same time. Therefore, there are many instances of each protocol. Each instance is associated with a state. For instance in TCP, the position of the recent acknowledged data needs to be kept. Most of the protocols require action when either an item of the stream or request occurs - for instance the reception of an IP packet - or when a certain time after such an event has elapsed. The required action can be implemented in software or hardware dependent on the complexity and data space. Furthermore, hybrid implementations are known where the frequent cases are processed by hardware while the remaining cases with high complexity like opening a new stream or handling an error are delegated to software.

This disclosure is related to a block of configurable logic integrated into a larger device for the execution of communication protocols. It is assumed, that there is an environment which handles the scheduling of the processing of the incoming packets and expired "time outs", the organization of memory for holding the state of the individual streams as well as initialization and error processing. This environment is illustrated in the following figure:

Incoming packets are scheduled for individual processing on the programmable logic core. The scheduler could be as simple as a first-in first-out buffer. For the processing of the next packet the store management is incorporated which maintains tables of states with respect to the processed protocol organized for the individual streams. The protocol state store can be divided into on-chip and off-chip store for improved power, area and performance efficiency. The access of the store and the processing in the core can be pipelined to increase throughput. The result of protocol processing in the programmable logic core consists of packet commands, time management commands (such as starting a new time-out period or deleting an existing one) and state updates. Packet commands include the alteration, duplication, creation or deletion of packets.

Time management

Incoming Packets

Outgoing Packets

 Packet Alteration

Programmable

  Logic Core for Protocol Processing

  Store Managment

 Protocol State Store

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Furthermore, other processing resources like a micro processor (core) can be assigned. The connection of the environment to the programmable logic core can be done in two ways: either all related signals can be routed to or some signals (i.e. packet header data) is multiplexed, that is accessed like memory. Two selected signals "start" and "ready" are of special importance. The "start" net is driven by the environment an...