Browse Prior Art Database

Mini Rings around core in semiconductor IC to reduce die-size

IP.com Disclosure Number: IPCOM000010717D
Original Publication Date: 2003-Jan-15
Included in the Prior Art Database: 2003-Jan-15
Document File: 5 page(s) / 34K

Publishing Venue

Motorola

Related People

Chetan Verma: AUTHOR [+3]

Abstract

A technique to reduce the die size of a semiconductor IC is proposed. The proposed technique talks about “pre-inserting” two minimum width metal rings around the core in the ‘io-to-core’ region. The “pre-inserted” rings help eliminate the irregular and indisciplined routing in the io-to-core region. This frees up a lot of routing tracks in that region thereby resulting in the die-size reduction.

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Page 1 of 5

Mini Rings around core in semiconductor IC to reduce die-size

Chetan Verma Milind Padhye

Sahil Dabare

Abstract

A technique to reduce the die size of a semiconductor IC is proposed. The proposed technique talks about "pre-inserting" two minimum width metal rings around the core in the 'io-to-core' region. The "pre-inserted" rings help eliminate the irregular and indisciplined routing in the io-to-core region. This frees up a lot of routing tracks in that region thereby resulting in the die-size reduction.

copyright Motorola, Inc, 2002 1 of 5

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Introduction

With increasing compaction of functionality in the same chip, IO rings are becoming more and more complex. The IO rings can now have major reconfiguration capability. IO cells used inside the padring are thus having multiple pins to enhance reprogram options. In most cases, these pins of IO cells are tied to power , ground and configuration logic. Demand for tracks in IO to core space thus increases and this causes a major congestion in that region. Due to the above mentioned problems, IO to core spacing is increasing in SoCs to accommodate increased connectivity needs.

The innovation is targeted toward solving this problems by pre-inserting two mini rings in IO to core space (one for power and other for ground). As these rings could be of minimum width, they consume only two tracks through out the IO to core space, thereby, making way for die-size reduction.

copyright Motorola, Inc, 2002 2 of 5

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The following figure illustrates the scheme:

A tie-high iopin

A tie-low iopin

IO

IO

IO

IO

IO

IO

CORE

IO

IOIO

IO

IO

IO

VDD ring

VSS ring

copyright Motorola, Inc, 2002 3 of 5

[This page contains 2 pictures or other non-text objects]

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Description of the proposed technique

The figure above shows a brief view of a chip which has core area and the io area as defined. The region between the core boundary and the dotted boundary, as sh...