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A High-Efficiency Handshaking Strategy for Quasi-Delay Insensitive Circuits

IP.com Disclosure Number: IPCOM000010728D
Publication Date: 2003-Jan-15
Document File: 4 page(s) / 155K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a strategy for designing Quasi-Delay Insensitive (QDI) circuits. Benefits include reduced electrical redundancy and decreased logical stage count.

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A High-Efficiency Handshaking Strategy for Quasi-Delay Insensitive Circuits

Disclosed is a strategy for designing Quasi-Delay Insensitive (QDI) circuits. Benefits include reduced electrical redundancy and decreased logical stage count.

Background

Current QDI circuits typically use the precharge halfbuffer template.� QDI requires synchronization of all input and output data signals as a flow control mechanism that regulates when new computations can begin; this implies long pFET chains for the simplest implementations (i.e. weak-condition logic). This approach is generally unfeasible and necessitates switching to domino outputs with additional parallel circuitry to compute input validity. The specifics of this circuitry are the chief factor governing performance and efficiency.

A key element is the number of logical stages (or transitions) needed to complete the four phase handshake on inputs and outputs. This is an increasing function of the number of inputs and outputs being synchronized, where complicated logic blocks require complicated handshaking.� Assuming that average transition time is constant and pipeline latency itself is not a limiter, this shows that shallow, complex pipelines have higher cycle times than deep pipelines with simpler stages.� Where pipeline latency is a limiter, that latency is two transitions (domino node and following inverter) per stage.

General Description

In the disclosed method, all dynamic nodes in QDI have staticizers (i.e. typically weak cross-coupled inverters) attached. Also, the external loads are not so large that adding inverter pairs will boost throughput (i.e. that minimal handshake transition count is optimal).� Solving such large loads by bloating the transition count with buffering, or by employing deeper pipelining to fan down the loads, may be accomplished by the existing and proposed circuits, and is irrelevant to the disclosed method.

For the sake of simplicity, all data channels use dual-rail, return-to-zero encoding and a single enable signal. Production rule notation, used below, is in the form (Boolean) -> transition; where transition is a Boolean variable followed by either a + or – ,indicating a shift to true or false, triggered by the Boolean evaluating to true. As with current solutions, each data signal in the disclosed method’s output function F is implemented by the following domino operator, as shown in Figure 1:

� Oe&en&F(inputs) -> output# valid

� !Oe&!en� � � � � � � � � � � � �...