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Method for soldering capacitor arrays under BGAs to improve decoupling capacitance

IP.com Disclosure Number: IPCOM000010797D
Publication Date: 2003-Jan-22
Document File: 5 page(s) / 145K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for soldering capacitor arrays under ball-grid arrays (BGAs) to improve decoupling capacitance. Benefits include improved performance.

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Method for soldering capacitor arrays under BGAs to improve decoupling capacitance

Disclosed is a method for soldering capacitor arrays under ball-grid arrays (BGAs) to improve decoupling capacitance. Benefits include improved performance.

Background

              Single 0402 (1.0-mm x .5-mm) rectangular-shaped surface-mount technology (SMT) capacitors are commercially available from several capacitor suppliers (see Figure 1). They are inexpensive components and are used in cell phone boards.        

              Conventional BGA circuit designs are limited in the capacitance that can be inexpensively placed in the immediate vicinity of the die. Some prototype solutions exist for placing single 0402 capacitors in the second-level interconnect area (see Figure 2). However, this solution does not offer the greatest capacitance density that may be required in next-generation silicon designs.

              Conventional solutions use individual capacitors on top of the BGA substrate or on the motherboard. This technology enables easy capacitor assembly but has a longer electrical path that reduces the benefits of the capacitors in the circuit design. One solution uses capacitors placed outside of the direct DC current path on the motherboard or substrate (see Figure 3). This approach results in a longer inductance loop that limits capacitor effectiveness.

General description

      The disclosed method is the soldering of 0402 capacitor arrays at the second-level interconnect between the BGA and motherboard. The capacitor array is placed on the package bottom to provide high-density capacitance close to the silicon.

              The disclosed method enables capacitors to be placed directly next to each other in a .5-mm x 1-mm pitch grid pattern by using arrays that are available commercially and inexpensively in .5-mm pitch arrays. The disclosed method delivers twice the capacitance density between the BGA and motherboard when compared to a prototype design. The capacitor array is 4 individual 0402 capacitors that are jointed together to make a .040-in. x .080-in. package with 8 solder terminals. The disclosed method doubles the capacitor density within the DC current path.

      The key element of the method is the attachment process of a 1.0-mm x .5-mm capacitor array soldered at the second-level interconnect.

Advantages

              The disclosed method provides advantages, including:

•             Improved performance due to an improved inductance loop because the 0402 capacitor array is placed directly in the path of the DC current loop

•             Improved cost effectiveness due to the use of 0402 capacitors

Detailed description

      The disclosed method is the soldering of capacitor arrays under BGAs to improve decoupling capacitance. The pitch of the BGA and motherboard pads change from 1 mm to .5 mm at the capacitor array to accommodate the increased capacitance density (see Figure 4). This change occurs because the capacitor array is at a .5-mm pitch...