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Method for NMI assertion on a PERR# event

IP.com Disclosure Number: IPCOM000010806D
Publication Date: 2003-Jan-22
Document File: 1 page(s) / 84K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for nonmaskable interrupt (NMI) assertion on a parity error (PERR#) event. Benefits include improved functionality and improved ease of implementation.

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Method for NMI assertion on a PERR# event

Disclosed is a method for nonmaskable interrupt (NMI) assertion on a parity error (PERR#) event. Benefits include improved functionality and improved ease of implementation.

Background

              Conventionally, no chipset input/output controller hubs (ICHs or P64Hx) are able to assert an NMI when a data-parity miscomparison occurs on a bus segment. Possible solutions include creating a custom product and a BIOS workaround, which introduces a long latency between the time the PERR# is asserted and NMI is activated.

Description

              The disclosed method is NMI assertion on a PERR# event. The method is a board-level change that ties the PERR# directly to the NMI. Some voltage levels translation is required because the NMI and PERR# signals are not of the same type. The change in voltage can be achieved in a number of ways. A simple way is to use a field-effect transistor (FET) to pull the NMI signal high whenever PERR# is asserted, thereby shutting down the system (see Figure 1).

              Advantages

              Some implementations of the disclosed structure and method provide one or more of the following advantages:

•             Improved functionality due to tying the PERR# and the NMI

•             Improved ease of implementation due to the simplicity of the solution

Fig. 1

Disclosed anonymously