Browse Prior Art Database

XOR-Network for LBIST and LFSR-Coding

IP.com Disclosure Number: IPCOM000010840D
Original Publication Date: 2003-Jan-24
Included in the Prior Art Database: 2003-Jan-24
Document File: 5 page(s) / 28K

Publishing Venue

IBM

Abstract

This paper concerns VLSI manufacturing test in scan chain design. It describes a hardware and method for 1) generating pseudo random patterns in parallel for Built-in Selftest (LBIST) and 2) for expanding test vectors for compressed stored pattern testing (LFSR-Coding). The novel XOR-network supplies a multiple of scan chains required for LBIST. It reduces the noise and enables more efficient LFSR-Coding. The advantages are demonstrated by simulation runs in comparison to conventional hardware.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 29% of the total text.

Page 1 of 5

XOR-Network for LBIST and LFSR-Coding

The disclosure pertains to so-called scan testing of VLSI chips, on which test data is loaded by scan-load operations into internal shift register latches (SRLs) to stimulate the chip for testing. It concerns the two basic test approaches, namely Deterministic Stored Pattern Testing (DSPT) and Built-in Selftest (BIST), which in common VLSI manufacturing tests are both part of a comprehensive test procedure supplementing each other.

   Considering the increase of chip size the following two problems are emergent and grow both more than proportionally:
1) For DSPT the volume of stored test data.
2) For BIST the test application time. As a consequence there are several suggestions how to reduce stored test data volume for DSPT and to accelerate random pattern generation for BIST. In this context so called LFSR-Coding is under discussion. This method is characterized by the fact that expansion of compressed test data is done by the very same hardware structure already available for LBIST. However, in the light of the novel LFSR-Coding the common LBIST hardware appears to be quite inefficient. Here the problem arises that a hardware for both, fast LBIST and efficient LFSR-Coding is required but not available so far.

    Fig. 1 shows the basic hardware structure for pseudo random pattern generation for parallel LBIST. The Linear Feedback Shift Register (LFSR) generates a certain pseudo random pattern, and the XOR-network combines a mixture of random bits out of the LFSR's via exclusive OR gates (XOR). Thus the output is a multiple of parallel random patterns. In other words, the one original random pattern is transformed into a multiple of different random patterns for a number of parallel scan chains. The pattern transformation by XOR-network is subject of this paper.

LFSR

+ o

1

2

3

4

5

6

7

XO R -netw ork

parallel scan ch ain s

F ig u re 1: X O R -N etw o rk fo r P arallel L B IS T

    A typical XOR-network for supplying a multiple of scan chains is the so called STUMPS architecture. It is characterized by a multiple connection of the first LFSR position - the one that contains the last value of the LFSR feedback line - to all XOR gates in parallel. However, to connect one LFSR-bit to all XOR has two disadvantages: it causes electrical noise because of the high load of this line, and the output patterns of the XOR are somehow concurrent. The latter is subject of several papers which mostly conclude, that such 'linear dependencies' have none or

[This page contains 2 pictures or other non-text objects]

Page 2 of 5

little impact on the efficiency of LBIST. Be that as it may, for LFSR-Coding such linear dependency are very destructive. This is demonstrated simulation runs as shown below.

    The basic idea of this novel XOR-network is a set of rules for designing it with regard to the theory of LFSR-Coding such that LFSR-Coding works most efficiently. In other words, the way how LFSR-Coding works implies a specific arr...