Browse Prior Art Database

Method for instruction cache coherence on a processor with disjoint level-2 caches

IP.com Disclosure Number: IPCOM000010890D
Publication Date: 2003-Jan-29
Document File: 4 page(s) / 95K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for instruction cache coherence on a processor with disjoint level-2 caches. Benefits include improved functionality and improved performance.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 50% of the total text.

Method for instruction cache coherence on a processor with disjoint level-2 caches

Disclosed is a method for instruction cache coherence on a processor with disjoint level-2 caches. Benefits include improved functionality and improved performance.

Background

              General-purpose caches are designated by level, such as L0, L1, and L2 for level 1, level 2, and level 3 caches. Instruction-only caches are designated by the level immediately followed by the letter I, such as L0I, L1I, and L2I for level 1, level 2, and level 3 instruction-only caches (see Figure 1). Data-side caches are designated by level and with the letter D, such as L0D and L1D. The level-3 unified cache is designated as L2.

              Implementations that enhance a single level instruction-only cache to a two level (L0I, L1I) instruction-only cache simplify the instruction-side snoop mechanism. These implementations invalidate the L0I and L1I caches for all types of snoops (such as snoop-to-invalidate and snoop-to-share). As a result, an unnecessary L0I, L1I line invalidation on a snoop-to-share leads to a processing penalty of an L2 access.

General description

              The disclosed method is instruction cache coherence on a processor with disjoint level-2 caches. The method maintains the coherence of the lower level instruction-only caches. For simplicity, this disclosure describes the method, illustrating only three levels of caches. The method can be expanded to include multiple levels of cache hierarchy.

              The disclosed snoop mechanism applies to the modified exclusive shared and invalid (MESI) cache coherency system. A processor inquire-cycle hit/miss (HITM) to a modified line results in an implicit write back (WB) on the bus and the invalidation of the local copy.

Advantages

              The disclosed method provides advantages, including:

•             Improved functionality due to filtering snoops directed to L0I and L1I caches, supporting improved cache utilizations with multi-threading and multi-core implementations

•             Improved performance due to preventing the penalty of an L2 access because of the unnecessary invalidation of I-side cache lines with the share probes of simple mechanisms

•             Improved performance due to reducing the number of L0I and L1I invalidation snoops to only the case of processor HITM with some processors designed for multi-node systems and with L2 cache that is inclusive of L0I and L1I caches

•             Improved performance due to reducing the cache invalidation traffic by eliminating it under the case of processor HITM with L2 cache misses with some processors designed for multi-node systems and with l2 cache that is inclusive of L0I and L1I

             

Detailed description

              The disclosed method is an enhanced cache coherence mechanism for L1I caches (see Figure 2). The method includes a snoop mechanism for a processor with a unified level-3 cache and disjoint level-1 and level-2 caches (see Figu...