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Method for a PCI-Express read/write request pipeline stage availability-based fair and scalable arbitration scheme

IP.com Disclosure Number: IPCOM000010975D
Publication Date: 2003-Feb-05
Document File: 7 page(s) / 118K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a PCI-Express read/write request pipeline stage availability-based fair and scalable arbitration scheme. Benefits include improved performance and improved design flexibility.

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Method for a PCI-Express read/write request pipeline stage availability-based fair and scalable arbitration scheme

Disclosed is a method for a PCI-Express read/write request pipeline stage availability-based fair and scalable arbitration scheme. Benefits include improved performance and improved design flexibility.

Background

              PCI Express defines a packetized protocol and load/store architecture. PCI Express is a trademarked name owned by PCI-SIG. Specification 1.0 was released on July 23, 2002. PCI_Express protocol specifies separate credit-based flow control for reads and writes.

              PCI Local Bus Specification version 2.3 (PCI v2.3) released March 20, 2002 is a trademark of PCI-SIG.

      Conventional round robin arbiters do not enable read requests from independent sources to pass write requests when no write credits exist or vice versa.

              Infiniband is a trademarked name owned by Infiniband Trade Assn. Specification 1.0 has a release date of October 24, 2000.

              In conventional versions of host interfaces, only one pipeline occurs at the output of the arbiter. The request flow using PCI and PCI-Express pipelines is based on different flow control credit information (such as nonposted read requests and posted write request credits) of the PCI-Express transaction layer. These two separate pipeline flows must be handled in a way that is efficient and fair.

              In the conventional round-robin solution, the number of request sources is designated as N. The sources are arranged in ascending order with source IDs from 0 to N-1. The state machine, which has just one pipeline output, assigns priority to each request source in a strict order-based method on the recently selected source (agent). The currently selected source is assigned the least priority. By order of arrangement, the source next to the currently selected one is assigned the highest priority with a decreasing order of priority to the sources that follow. For example, if source 3 is currently selected, source 4 is assigned the highest priority. Source 5 is the second highest priority. Subsequent sources receive decreasing priorities. This decreasing order of priority wraps back to source 0 after N and continues decreasing as the source ID increases from 0 to the currently selected source with source 2 receiving the lowest priority.

General description

              The disclosed method is PCI-Express read/write request pipeline stage availability-based fair and scalable arbitration logic. The method is utilized by a part of a chip that is a host channel adapter implementing the Infiniband protocol. Independent request sources (agents that do not have any PCI ordering dependency between each other’s requests) generate read or write requests. One request at a time is selected by the arbitration logic for presentation to the PCI-Express transaction layer. It has two pipelines through which these requests are routed, one pipeline for read requests a...