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Method for a package using wirebond and flip-chip interconnects with silicon vias

IP.com Disclosure Number: IPCOM000011431D
Publication Date: 2003-Feb-19
Document File: 4 page(s) / 144K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a package using wirebond and flip-chip interconnects with silicon vias. Benefits include improved power performance and improved design flexibility.

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Method for a package using wirebond and flip-chip interconnects with silicon vias

Disclosed is a method for a package using wirebond and flip-chip interconnects with silicon vias. Benefits include improved power performance and improved design flexibility.

Background

              Some chipset or communications die are pad-limited. The die area must be expanded to allow sufficient perimeter wirebond pads to route all signals, power, and ground wires to the substrate. As wirebond pitch is decreased to improve input/output (I/O) density, crosstalk issues between adjacent wires increase. Decreased wirebond pitch may also drive the use of smaller wirebond wire diameters, leading to reduced current carrying capability and a requirement for more wires, defeating the purpose of increased density.  In the flip-chip case, bump pitch or substrate routing limitations may prevent all I/O from being routed without growing the die or adding substrate layers.

              Conventionally, the die may be 100% wirebonded, which can lead to pad-limited designs where the die area is grown to accommodate sufficient perimeter wirebond pads, wasting silicon. Alternatively, the die may be 100% flipchip. In the flip-chip case, difficulty in routing the I/O on the package can result as density demands increase. This situation can also lead to larger bump pitches and a larger die size than is optimal.  A ball-grid array (BGA) substrate is an example of a conventional method (see Figure 1).

General description

              The disclosed method is integrated circuit (IC) packaging utilizing mixed technology of wirebond and flip-chip die-to-package interconnects to enable electrical connection on both sides of the die. One side of the die is flip-chip attached and the other side is wirebond attached to the substrate. The backside of the die is electrically connected to the frontside (active side) through silicon vias. This approach enables the power and I/O connections to be isolated and enables higher I/O density than standard wirebond or flip-chip package technologies.

              The addition of silicon vias and bottom side flip-chip joints to perimeter topside wirebonds for carrying power, ground, and selective I/O can eliminate the pad-limited situation. Power can be delivered to central areas of the die without using traces from the perimeter of the die to the center. This approach further improves silicon utilization and may enhance die performance.

              In the case of stacked-die configurations, the bottom die could provide power to the top die through the via and bump structure, improving routing within the package.  The disclosed method is not limited to BGA substrates. It applies to other substrate technologies as well.

              The key elements of the method include:

•             Silicon vias through a thinned die enabling the frontside and backside of the die to be utilized for power and I/O routing from the die to the substrate

•             IC package die connected...