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Method for TPT cache-line locking in a multi-threaded HCA

IP.com Disclosure Number: IPCOM000011436D
Publication Date: 2003-Feb-19
Document File: 4 page(s) / 39K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for translation and protection table (TPT) cache-line locking in a multi-threaded host channel adapter (HCA). Benefits include improved performance and improved reliability.

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Method for TPT cache-line locking in a multi-threaded HCA

Disclosed is a method for translation and protection table (TPT) cache-line locking in a multi-threaded host channel adapter (HCA).� Benefits include improved performance and improved reliability.

Background

        � � � � � InfiniBand is a trademarked name owned by InfiniBand Trade Assn. Specification 1.0 release date October 24, 2000) is an industry standard for a channel-based, switched fabric, interconnect architecture for servers.� InfiniBand Architecture (IBA) utilizes large amounts of system memory for holding many kinds of control information.� For an HCA to store and retrieve information from system memory, the physical memory address must be determined.� Many functions within the HCA core implement virtual memory addressing, which provides large contiguous blocks of memory addressing space.� Typically, the memory addressing spaces used by HCA core functions do not map 1-to-1 with system memory addressing space.� The procedure of mapping HCA virtual address spaces to system physical address space is called address translation.

        � � � � � The large contiguous memory addressing space used by HCA functions is mapped to multiple pages of system memory addressing space.� HCA (virtual address) pages are the same size as the system pages and are always contiguous.� However, the system pages may or may not be contiguous.� As a result, address translation must occur every time a memory page boundary is crossed.� An address translation returns the base address of the equivalent system page.� The HCA then uses the base address with a local offset for all accesses within the page.

        � � � � � One issue with conventional address translation is that it is latency sensitive.� HCA address translations require one or more accesses to system memory during which time hardware waiting for the translation result must wait.� In InfiniBand, the hardware is required to perform the virtual to physical address translation.� Each time a page boundary is encountered the host channel adapter must perform a translation from a virtual address to the actual physical address.� Because InfiniBand places no restrictions on the physical addresses being contiguous, this operation must be performed at each page boundary (see Figure 1).

        � � � � � To reduce the latency penalty for accessing host memory each time a virtual-to-physical address translation is required, a high-performance host channel adapter may implement a cache for the address-mapping table.� Most operations to the table are read only.� A problem can occur when the HCA is operating on many different threads that may all a...