Browse Prior Art Database

Method for an optimally partitioned hardware sequencer comprised of a controller and datapath to assemble InfiniBand work requests

IP.com Disclosure Number: IPCOM000011522D
Publication Date: 2003-Feb-26
Document File: 8 page(s) / 98K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for an optimally partitioned hardware sequencer comprised of a controller and datapath to assemble InfiniBand work requests. Benefits include improved functionality and improved design simplicity.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 19% of the total text.

Method for an optimally partitioned hardware sequencer comprised of a controller and datapath to assemble InfiniBand work requests

Disclosed is a method for an optimally partitioned hardware sequencer comprised of a controller and datapath to assemble InfiniBand work requests. Benefits include improved functionality and improved design simplicity.

Background

        � � � � � InfiniBand is a trademarked name owned by InfiniBand Trade Assn. Specification 1.0 (rel. date 10/24/2000) is an industry standard for a channel-based, switched fabric, interconnect architecture for servers.        � � � � � � � � � � � � � � � � �

        � � � � � InfiniBand Architecture includes a packets-based interconnect technology for point-to-point data communication. The endpoints communicate through queue pairs (QPs) comprised of a send queue (SQ) and a receive queue (RQ). When the QP is created, the QP context is programmed. The QP context has number of fields used to move the data from the SQ to RQ.� The QP transmits and receives messages through a port on the channel adapters. The minimum bandwidth for the port of the InfiniBand channel is 2.5 Gb/sec. The port used to move the data is programmed in the QP context.

        � � � � � In this host channel adapter (HCA) chip, the QP context resides off the chip in the side random access memory (side-RAM). The purpose of this memory is to hold the QP context data for the large number of QPs. The dedicated interface for the side-ram provides faster access to the QP context memory from HCA. The QP context is divided into five groups of 32 bytes each. The QP context memory is divided into groups to enable different clusters/fubs in the message engine cluster (MEC) process different groups simultaneously.

The MEC cluster assembles the work request and passes it downstream to transmit packet cluster (TPC). The work request is comprised of the fields that are present in InfiniBand messages. The TPC builds the InfiniBand messages. The MEC is comprised of the scheduler link list doorbell (SLD), transmit request generator (TRG), work queue element (WQE)/address vector table (AVT) command engine (WAC), transport resource timer (TRT), context data store (CDS) and command and exception processor (CEP) fubs.

        � � � � � The HCA supports up to 256K QPs and has two physical ports designated as Port0 and Port1. Each port supports 4 virtual lanes (VL) VL0, VL1, VL2, VL3, and the mandatory VL15. Several QPs can use the same port and VL to transmit messages. A linked list is built to track the QPs that have messages to transmit on the port and VL. The HCA can have 5-linked lists, called transmit linked lists, for each port.

        � � � � � The SLD block adds the QPs to the link list. The TRG block reads the head of the link list. Then the TRG builds the work request for the QP message to send it downstream to the transmit TPC.

        � � � � � The SLD maintains the link-lists so that a QP is present on only one of the link lists. The HCA has two TPCs, one for each port. The TPC...