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Method for integrated chipset support for an untranslatable I/O channel

IP.com Disclosure Number: IPCOM000011524D
Publication Date: 2003-Feb-26
Document File: 5 page(s) / 91K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for integrated chipset support for an untranslatable input/output (I/O) channel. Benefits include improved functionality, improved reliability, improved design flexibility.

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Method for integrated chipset support for an untranslatable I/O channel

Disclosed is a method for integrated chipset support for an untranslatable input/output (I/O) channel. Benefits include improved functionality, improved reliability, improved design flexibility.

Background

              Advanced Configuration and Power Interface (ACPI) specification version 2.0.b is an open industry specification released November 11, 2002.

              I2C is a trademark of Philips Semiconductors. The I2C Bus specification version 2.1, was released January 2000.

              PCI is a trademark of PCI-SIG, The PCI Local Bus Specification version 2.3 (PCI v2.3) was released March 20, 2002.

              System Management Bus (SMBus) Specification version 2.0 was released August 3, 2000 by the Smart Battery Systems Implementers’ Forum (SBS IF).

General description

              The disclosed method is integrated chipset support for an untranslatable I/O channel. The method provides support for a communications channel that the operating system cannot reconfigure without violating platform architecture specifications and without requiring I/O manager/driver changes. The method supports system software communication and debugging independent of the system fabric, I/O bus, and the operating system.

              The key elements of the method include:

•             Translation that is transparent to the operating system (OS) and industry standard platform descriptions
•             Support for the deprecation of serial DB9 headers because they are predominately used for debugging

Advantages

              Some implementations of the disclosed structure and method provide one or more of the following advantages:

•             Improved functionality due to enabling communication, error messaging, and debugging capabilities for firmware

•             Improved reliability due to the availability of realtime device addressing rather than information detected by the OS at startup

•             Improved design flexibility due to the capability to deploy software state machine communications in various stages of the firmware evolution

•             Improved cost effectiveness due to a negligible cost to implement a major variation on silicon

Detailed description

              The disclosed method is integrated chipset support for an untranslatable I/O channel. The method supports early debugging and a mechanism that is not controlled by the operating system. The disclosed method (see Figures 1) uses general-purpose input/output (GPIO) pins that are decoded by the memory-mapped firmware hub (FWH) or another application-specific integrated circuit (ASIC), such as the input/output controller hub (ICH). It memory-maps the firmware region near 4GB to enable a bidirectional communications channel from firmware for source-level debug, error messaging, manufacturing/test support, and realtime system configuration.

              The disclosed method uses two general-purpose input/output (GPIO) pins and leverages the part...