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Browse Prior Art Database

Pipeline control for a low-power microprocessor

IP.com Disclosure Number: IPCOM000011581D
Original Publication Date: 2003-Mar-06
Included in the Prior Art Database: 2003-Mar-06
Document File: 1 page(s) / 40K

Publishing Venue

IBM

Abstract

According to the present invention, information about the success (or lack thereof) of executing an instruction in accordance with the teachings described in US Patent 6192466 is used to reduce power dissipation by de-energizing pipeline stages executing instructions which are indicated as having to be re-issued. In one embodiment, this is achieved by clock-gating substantial portions (or all) of a pipeline stage currently executing an instruction being associated with said indicator.

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YOR820011274 Louis J Percello/Watson/IBM Michael Gschwind, Stephen Kosonocky

Pipeline control for a low-power microprocessor

Pipeline interlock management is important to achieve compatibility across multiple genererations to deal with variable latency operations to avoid excessive NOP operations to cover long-latency operations to deal with compiler immaturities which may not always produce 100% perfect schedules (in a non-interlocked processor, this can have disastrous results)

Traditional pipeline management based on a central controller tracking the pipeline is complex because it requires complex tracking of instructions in the pipeline and keeping track of all pogtential inter-lock sceneriosd
error-prone because this logic is hard to verify slow because time for long wire delays across the pipeline have to be allocated in all processor cycles

In addition, complex control logic may have high power consumption, driving global communication requires power (buffers, fat wire, etc), clock gating from a central controller can complicate logic even more.

In related art, US Patent 6192466 discloses a novel method for implementing a distributed pipeline management scheme. According to the present invention, the indicators described in said invention to force re-execution of one or more instructions are also used to reduce the power dissipated in pipeline stages which are forwarding an ins...