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Integration Scheme For Germanium Based Device Applications

IP.com Disclosure Number: IPCOM000011604D
Original Publication Date: 2003-Mar-07
Included in the Prior Art Database: 2003-Mar-07
Document File: 4 page(s) / 1M

Publishing Venue

Motorola

Related People

Craig Jasper: AUTHOR [+2]

Abstract

Implantation and activation of Germanium based devices has been a challenge for over 40 years. Historical publications indicate that the electrical activation of germanium was very difficult to control. Very few details have been published about the outgassing, activation, and passivation of single crystal germanium substrates. These publications indicate that there is a large amount of dopant loss during the activation process. However, the processing and experimental details are either not given or they are incomplete. From these publications it is unclear if the dopant is segregating into the oxide, or evaporating from the substrate. In either case the result is the same, a lack of active carriers within the material.

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Integration Scheme For Germanium Based Device Applications

Craig Jasper and Mike Kaneshiro

Implantation and activation of Germanium based devices has been a challenge for over 40 years. Historical publications indicate that the electrical activation of germanium was very difficult to control. Very few details have been published about the outgassing, activation, and passivation of single crystal germanium substrates. These publications indicate that there is a large amount of dopant loss during the activation process. However, the processing and experimental details are either not given or they are incomplete. From these publications it is unclear if the dopant is segregating into the oxide, or evaporating from the substrate. In either case the result is the same, a lack of active carriers within the material.

There are distinct advantages that can be obtained when both silicon and germanium devices are present on the same die. However, this also presents some very challenging integration issues. Publications on germanium activation indicate that boron activates at ~400C and phosphorus activates at temperatures ~500C.1 These low temperatures are not conducive to a typical silicon front end processing, where activation temperatures are in the 900 to 1000C range. Germanium substrates also exhibit a large amount of dopant or substrate loss during the activation process even at these low temperatures. See Figure #1. From this figure the loss of dopant is clearly shown by Secondary Ion Mass Spectroscopy analysis of a germanium annealed samples. To prevent the dopant loss or sublimation of germanium a capping layer of a dense material is required to protect the germanium surface. It has been demonstrated that thick films of SiO2 will not provide an adequate capping material for implanted germanium.2 Therefore, integration of low temperature germanium doping processes must be done after the formation of CMOS transistors, where lower temperatures are prevalent.

The integration of germanium type devices is performed after the typical silicon CMOS source/drain implants and salicide contacts regions are formed. This is due to the low activation temperatures and sublimation of germanium. A metal capping layer or other dense material would be used as a barrier during the integrated circuit manufacturing process to prevent the sublima...