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Digital Reset-Based State Machine Synchronizer

IP.com Disclosure Number: IPCOM000011621D
Original Publication Date: 2003-Mar-10
Included in the Prior Art Database: 2003-Mar-10
Document File: 4 page(s) / 74K

Publishing Venue

Motorola

Related People

Hector Ricardo Sucar: AUTHOR

Abstract

State machines are commonly used structures in the design of integrated circuits to implement control and data generation functions. Most state machines are synchronous mechanisms defined to provide a specific sequence of states. Setting and maintaining state machine sequence synchronization is a requirement for correct system operation. This work presents a new method for implementing self-synchronizing state machines with negligible performance impact. The synchronization approach is independent of the actual state machine logic implementation. Hence, optimal performance may be achieved. The synchronization method provides a power-on-reset-type capability to set initial synchronization and constantly verifies sequence correctness through the operation of the device providing synchronization recovery if necessary. Thus, maintaining state machine synchronization. The implementation is fully digital and it could be built using standard IC technologies (CMOS, BiCMOS, Bipolar, etc.).

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Digital Reset-Based State Machine Synchronizer

Hector Ricardo Sucar

Abstract

State machines are commonly used structures in the design of integrated circuits to implement control and data generation functions. Most state machines are synchronous mechanisms defined to provide a specific sequence of states. Setting and maintaining state machine sequence synchronization is a requirement for correct system operation. This work presents a new method for implementing self-synchronizing state machines with negligible performance impact. The synchronization approach is independent of the actual state machine logic implementation. Hence, optimal performance may be achieved. The synchronization method provides a power-on-reset-type capability to set initial synchronization and constantly verifies sequence correctness through the operation of the device providing synchronization recovery if necessary. Thus, maintaining state machine synchronization. The implementation is fully digital and it could be built using standard IC technologies (CMOS, BiCMOS, Bipolar, etc.).

Algorithm

Assuming a state machine with a given state sequence, a specific state, or a specific transition between two states, represents a state alignment condition required to achieve system synchronization.

The common denominator of the state machine sequence may be defined as a bit sequence, derived from one or more of the state machine bit sequences, which determines a synchronization condition by providing a pulse for every instance of a state alignment condition. Hence, this pulse becomes part of the alignment (from now own referred to as the synchronization pulse – SP).

If a common denominator sequence that provides an SP exists, then the SP can be used to ensure sequence alignment and state machine synchronization.

This approach provides a state machine synchronization scheme based on the use of an SP to validate proper state alignment or, otherwise, to apply a reset condition to restart state machine operation in order to gain proper alignment.

Implementation

The reset-based synchronizer should be designed according to the specific state machine application and the corresponding state sequence alignment requirements. A divide-by-2/4/6 data generator is used to illustrate a specific implementation of the synchronization scheme. This generator is used in a number of clock devices produced by the timing solution operation (TSO).

Figure 1 shows a schematic diagram of the generator including the common denominator function. Signals D2, D4, and D6 represent the primary state sequence. Signals D2NQ, D4NQ, D6NQ, D2NQB, D4NQB, and D6NQB are used for synchronization. Signals D12 and D12N represent the SP. The correct state sequence is as follows:

D2 D4 D6 D2N D4N D6N D12 D12N

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