Browse Prior Art Database

A Tapered Power Grid Design and Optimization Method

IP.com Disclosure Number: IPCOM000011626D
Original Publication Date: 2003-Mar-10
Included in the Prior Art Database: 2003-Mar-10
Document File: 6 page(s) / 71K

Publishing Venue

Motorola

Related People

Ravindraraj Ramaraju: AUTHOR

Abstract

With aggressive scaling of power supply for higher performance and reduced power dissipation, the sensitivity to the variation in the power supply is greatly increased and robustness of the power grid is essential. More metal layers are needed to route due to increased complexity of the microprocessor and the growing conflict between efficient use of metal for power grid and routing channels. This publication explores designing the power grid in a novel approach to minimize the usage of metal in a layer and have the same robustness of an uniform grid structure by progressively tapering the metal lines away from the contact point, known as a C4 contact point, for a microprocessor design with uniform current distribution.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 48% of the total text.

A Tapered Power Grid Design and Optimization Method

Ravindraraj Ramaraju

Abstract

With aggressive scaling of power supply for higher performance and reduced power dissipation, the sensitivity to the variation in the power supply is greatly increased and robustness of the power grid is essential.� More metal layers are needed to route due to increased complexity of the microprocessor and the growing conflict between efficient use of metal for power grid and routing channels.

This publication explores designing the power grid in a novel approach to minimize the usage of metal in a layer and have the same robustness of an uniform grid structure by progressively tapering the metal lines away from the contact point, known as a C4 contact point, for a microprocessor design with uniform current distribution.

Introduction

In each generation of microprocessor design with new technology, the power supply voltage is scaled aggressively for increasing the speed and lowering power dissipation, since this results in the threshold of the transistors being lowered, the transistors become very sensitive to variation in power supply.� The mismatch and variation in the power supply can induce noise in the signal and cause false evaluation or propagate false data.� So considerable effort is put into design of the power grid to ensure uniform power supply and to minimize the variation in the power supply across the microprocessor, such that it meets a defined DC drop target.

Currently the power grid is designed in two styles. The first is the power plane approach where the entire metal layer is assigned to a power supply with no routing channels in that metal layer. The second is the more prevalent approach, which is an uniform grid structure in each metal layer with a certain percentage of the total metal allocated for the power grid. Both these approaches have pros and cons. This paper discusses a novel approach to design a grid structure taking advantage of current density in the power lines.

Tapered Power Grid Design

In a microprocessor designed with C4 contact points, the power supply is brought in through the VDD and GND contact points distributed almost uniformly over the entire surface on the microprocessor.� The grid structure is hooked up to the C4.� For example,� in nine Metal layer designs, the footprint of a C4 contact point dictates width and pitch of the top two layers.� Similarly the bottom three metal layers width and pitch is dictated by the library cell element. The remaining metal layers are designed according to the routing channel congestion.� The current distribution and demand are mostly uniform except in few areas of the microprocessor.�

The current enters through the C4 contact pin and is uniformly distributed over the grid, represented by the figure 1.� It can be seen that current ‘i0’ entering the top metal layer branches into i1,i2,i3,i4 and these currents in turn get divided uniformly.� The current branches out uniformly since th...