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High Conductance ESD Structure using an NPN Transistor with an End Triggered Integrated Zener Diode.

IP.com Disclosure Number: IPCOM000011691D
Original Publication Date: 2003-Mar-11
Included in the Prior Art Database: 2003-Mar-11
Document File: 5 page(s) / 388K

Publishing Venue

Motorola

Related People

James Whitfield: AUTHOR

Abstract

This structure nearly doubles the conductance of the typically used NPN transistor based ESD devices with an integrated Zener diode. The current state of the art NPN, integrated Zener structures are constructed using a long length NPN transistor, with one sides of the base being narrowly spaced to the collector, forming the integrated Zener trigger region. This integrated Zener spacing controls the trigger voltage. In the current state of the art integrated structures, the integrated Zener region runs the length of the transistor where as in the new design, the trigger region is confined to one end. During snapback operation the integrated Zener turns off or only has a small amount of current flowing through it, effectively leaving only one side of the transistor to conduct an ESD event. For the new design, both sides of the base structures conduct, reducing the resistance by a two and nearly doubling the current handling capacity. For a given ESD performance level the device to can be made almost half as large, saving valuable chip area. Two possible base contact configurations are possible; one with the whole length of the NPN transistor having contacts, and the other with base contacts only at the end of emitter/base near the trigger is located. The advantage of the base contacts at the ends is that the total length of the device can be reduced by 20% for a typical application, but both double the over all performance.

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High Conductance ESD Structure using an NPN Transistor with an End Triggered Integrated Zener Diode.

James Whitfield

Abstract

This structure nearly doubles the conductance of the typically used NPN transistor based ESD devices with an integrated Zener diode. The current state of the art NPN, integrated Zener structures are constructed using a long length NPN transistor, with one sides of the base being narrowly spaced to the collector, forming the integrated Zener trigger region. This integrated Zener spacing controls the trigger voltage. In the current state of the art integrated structures, the integrated Zener region runs the length of the transistor where as in the new design, the trigger region is confined to one end. During snapback operation the integrated Zener turns off or only has a small amount of current flowing through it, effectively leaving only one side of the transistor to conduct an ESD event. For the new design, both sides of the base structures conduct, reducing the resistance by a two and nearly doubling the current handling capacity. For a given ESD performance level the device to can be made almost half as large, saving valuable chip area. Two possible base contact configurations are possible; one with the whole length of the NPN transistor having contacts, and the other with base contacts only at the end of emitter/base near the trigger is located. The advantage of the base contacts at the ends is that the total length� of the device can be reduced by 20% for a typical application, but both double the over all performance.

Details of invention

On Chip, electrostatic discharge (ESD) protection structures consume a substantial amount of chip area, adding to the die cost. The most cost effective ESD devices are ones that have high ESD performances. This invention improves the already high efficiency NPN based device with an integrated Zener. In the current state of the art integrated NPNs the trigger region is formed by extending the base region toward the collector along the length dimension of the base. By making the trigger region only at the end of the device, along the shortest dimension of the base, the conductance and it's current handling capacity is doubled for a given device size or keeping the ESD performance the same, the total area can be reduced nearly in half. Farther area savings can be made by only having base contacts near the trigger region.�

Shown in figure 1 are three possible designs; (a) Current state of the art NPN based structure with the integrated Zener along one EDGE or width dimension of the transistor, (b) the new END triggered structure with the base contacts running along the width of the device, and (c ) the new END triggered structure with the base contacts only at the end of the E...