Browse Prior Art Database

Method to handle burst packets using Secondary Buffers

IP.com Disclosure Number: IPCOM000011704D
Original Publication Date: 2003-Mar-11
Included in the Prior Art Database: 2003-Mar-11
Document File: 5 page(s) / 76K

Publishing Venue

Motorola

Related People

Suhas Mitra: AUTHOR [+4]

Abstract

The use of a Buffer descriptor ring and buffers on a per channel basis are central to implementing finite queuing system applications. The system comprises on incoming packets into the system that are put into a receive queue and serviced in turn. Queues form because resources are limited and buffering is therefore essential.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 14% of the total text.

Method to handle burst packets using Secondary Buffers



Authors


Suhas Mitra

Adwait Ketkar

Reginald Richardson

Todd Schaefer


Motorola Inc.,

GTSS FortWorth, TX


Abstract

The use of a Buffer descriptor ring and buffers on a per channel basis are central to implementing finite queuing system applications. The system comprises on incoming packets into the system that are put into a receive queue and serviced in turn.  Queues form because resources are limited and buffering is therefore essential.

The queue depth is a function of the arrival process:

·         How customers arrive e.g. singly or in groups (batch or bulk arrivals)

·         How the arrivals are distributed in time (i.e. interarrival time distribution)

·         Whether there is a finite population of customers or (effectively) an infinite number.

Bursty traffic can be defined as the scenario when packets are queued up to a point where the service rate cannot match up with the arrival rate. Hence in a finite queuing system incoming packets will be dropped whenever the queue is exhausted. To encounter this scenario the obvious approach will be to increase the Depth of the Buffer Descriptor Ring and buffers, which raises the bar of the queuing system in general. For speed constraints and low latency, Primary Buffer Descriptors are normally allocated on the most expensive memory part in a chip and the fastest bus available in general. Hence increasing Primary Buffer Descriptor Ring Depth may require heavy consumption of expensive memory (Internal Static RAM) and also may be impossible if numerous such channels are implemented in a system.

Our innovation is to segregate the queuing system into two parts, Primary Buffer Descriptor Ring and a Secondary Buffer Descriptor Ring. The Secondary Buffer Descriptor Ring can be made to reside on a different Bus occupying a less expensive memory like Static DRAM. An individual Secondary Buffer descriptor can be made to be of a smaller size than a Primary Buffer Descriptor. Hence substantial memory and cost savings can be gained.

The paper talks about an implementation geared towards a 3G UMTS platform and how the use of Secondary buffers has alleviated the usage of memory significantly. The processing/servicing of Secondary Buffers is also discussed, as they need a unique service algorithm. Note that use of Primary Buffers is truly a Stateless system (the servicing of a packet is independent of the existence of other packets of the system thereof). The usage of Secondary Buffers on the other hand moves the system from a Stateless system to a Quasi-Stateful system (the servicing of the Bursty packets is handled in a different fashion than non-bursty packets).  We also provide numbers tailored for our particular system in this paper.

Combining the above perspectives, our innovative solution can be used in applications that use finite queuing buffers that can potentially experience bursty conditions. The innovative memory allocation and cost saving measures can have implicat...