Browse Prior Art Database

Method for backside wafer processing for improved thermal performance

IP.com Disclosure Number: IPCOM000011741D
Publication Date: 2003-Mar-12
Document File: 2 page(s) / 47K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for backside wafer processing for improved thermal performance. Benefits include improved thermal performance and improved design flexibility.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 63% of the total text.

Method for backside wafer processing for improved thermal performance

Disclosed is a method for backside wafer processing for improved thermal performance. Benefits include improved thermal performance and improved design flexibility.

Background

        � � � � � Thermal conductivity must be improved from Si to packaging.

        � � � � � Conventionally, thermal conductivity is enhanced using solder thermal interface material (TIM) and plating. No backside patterning is utilized, and the wafer is full thickness and flat.

� � � � � Conventional processing results in a 2-dimensional surface to the plated backside material (see Figure 1). Heat passes through the bulk Si. Wafers curl when thinned to ~3 mil thickness.

General description

� � � � � The disclosed method is backside wafer processing for improved thermal performance. The backside of the wafer is etched in a pattern that matches the thermal map. A more thermally conductive material is plated onto the wafer. It may be left rough or plated until the surface is flat again.

Advantages

        � � � � � The disclosed method provides advantages, including:

•        � � � � Improved thermal performance due to the use of a material with improved thermal conductivity

•        � � � � Improved thermal performance due to improved conductivity because of an increased surface area on the backside

•        � � � � Improved design flexibility due to improved structure with wafer thinning to ~3 mil thickness

Detailed description

� � � � � The disclosed method is backside...