Browse Prior Art Database

Maximize Transfer Rates To/From FIFO-Based Devices on the PXA250 Memory Bus by Implementing “Dummy” Variable Latency I/O Devices and Utilizing a DMA Transfer

IP.com Disclosure Number: IPCOM000011747D
Publication Date: 2003-Mar-12
Document File: 3 page(s) / 213K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that uses a USB 2.0 chip on an embedded PXA250-based device. This provides a handheld with connectivity to a desktop PC, enabling the user to exchange files and other data with the device.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Maximize Transfer Rates To/From FIFO-Based Devices on the PXA250 Memory Bus by Implementing “Dummy” Variable Latency I/O Devices and Utilizing a DMA Transfer

Disclosed is a method that uses a USB 2.0 chip on an embedded PXA250-based device. This provides a handheld with connectivity to a desktop PC, enabling the user to exchange files and other data with the device.

General Description

In the disclosed method, the USB 2.0 chip sits on the PXA250 main memory bus configured as an asynchronous static memory device (see Figure 1). Because it is a FIFO-based chip, in order to transfer data to/from the device, the read/write strobe is de-asserted in between each access.� Because of this, the MSCxxx register is programmed to make the chip look like an SRAM-type device. However, the PXA250 architecture creates a large latency between each access to the chip (on the order of 400ns); there are only so many cycles available for PIO because the LCD DMA, bus arbitration, and others take up most of the cycles.� This has a negative impact on the overall throughput of data transfer.� Therefore, to optimize transfers to the device, a DMA transaction needs to occur.� For DMA transfers, the CPU core hands over the bus to the DMA engine, which can burst data to/from the device without interruption. This can eliminate the large latencies in between each transaction so long as the device on the bus is capable of “bursting” the data as the PXA250 requests it.

With chips requiring de-assertion of the read/write strobe for each beat of the burst, there is only one way to reap the benefits of the DMA burst transaction while still being able to communicate with the chip. This solution programs the RTx<2:0> bits in the MSCxxx register to “100” to make it “Variable Latency I/O” (VLIO).� By doing this, the PXA250 communicates in bursts with the chip by holding the chip select low, and de-asserting the read/write strobe in b...