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Method for “domino-style” microelectronic packaging

IP.com Disclosure Number: IPCOM000011835D
Publication Date: 2003-Mar-19
Document File: 8 page(s) / 148K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for “domino-style” microelectronic packaging. Benefits include improved functionality, improved performance, improved power performance, and improved design flexibility.

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Method for “domino-style” microelectronic packaging

Disclosed is a method for “domino-style” microelectronic packaging. Benefits include improved functionality, improved performance, improved power performance, and improved design flexibility.

Background

      Future high-performance dies are expected to contain brittle or fragile structures due to the shift towards low dielectric constant (low-k)interlayer dielectrics on the die. These dies must be packaged without imposing excessive mechanical stresses that can lead to failures. As a result, mechanically compliant interconnects have been developed as an alternative to the conventional controlled collapse chip connection (C4) bump layer at the die/package interface. However, typical compliant interconnect structures with a spring-like physical design suffer from an inherent conflict between mechanical and electrical performance. Great mechanical compliance leads to great electrical inductance and resistance with concurrent degradation of the electrical high-speed performance.

              No comprehensive solution to this problem exists. Conventional multichip modules (MCMs) combine two or more dies into a single package but the issue of mechanical compliance is not addressed. The approaches of system-on-package (SoP) and system-on-chip (SoC) encompass mixed-signal system design, including the integration of wireless components. However, thermal and mechanical issues are typically ignored.

General description

              The disclosed method is a packaging technology for creating complex microelectronic modules in an overall mechanically compliant interconnection scheme while enabling adequate high-speed performance for communication. It is a compliant high-speed approach.

              The key elements of the method include:

•             Tiling of dies of varying complexity, referred to as high-density and low-density dies, forming a modular computing platform

•             Mechanical compliance of interconnects for the protection of brittle or fragile high-density on-die structures

•             Contactless interconnection across the edges of dies, using one of the following:

              -             Radio frequency (RF) interconnects
-             Microwaves
-             Millimeter waves
-             Free-space optics

•             Matching of the coefficient of thermal expansion (CTE) of dies, enabling dimensional control

•             Low-density dies housing components related to input/output (I/O) and that are of relatively large physical dimensions, such as the following:

              -             Connectors
-             Distributed filters
-             Distributed antennae
-             Lenses
-             Lasers
-             Photodetectors
-             Passive alignment structures

Advantages

              The disclosed method provides advantages, including:

•             Improved functionality due to mixture of high-density and low-density dies

•             Improved functionality due to mating of dies based on different processing t...